EPM9560RI304-15 vs EPM9560RC304-15F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI304-15 sa pamamagitan ng Intel at EPM9560RC304-15F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560RI304-15 | EPM9560RC304-15F |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD | Multiple Array MatriX (MAX) with PIA interconnect |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/Os | 212 (216 per some datasheets) | — |
| Dedicated Inputs | 4 | 4 |
| Total Terminals | 304 | — |
| Package Code | HFQFP / S-PQFP-G304 | — |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) | — |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA | 16.6 ns (max) |
| Maximum Internal Frequency | 145 MHz | 117.6 MHz |
| Speed Grade | -15 | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) | — |
| I/O Logic Levels | 3.3 V or 5 V configurable | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | -40C to +85C (industrial) |
| Temperature Grade | Industrial (per Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) | — |
| Process Technology | 0.5 µm CMOS EEPROM | High-performance CMOS, EEPROM-based |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status - not stated in source] |
| Series | — | EPM9560 |
| Usable Gates | — | 12,000 |
| Core Supply Voltage | — | 5.0 V |
| User I/O Pins | — | 212 |
| Logic Array Blocks (LABs) | — | 16 (40 macrocells each) |
| Packhaging | — | RQFP-304 (304-pin Plastic QFP) |
| Programming Technology | — | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Level ng MSL | — | 3 (168 hours) |