M1AFS250-PQ208 vs M1AFS250-1PQ208 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng M1AFS250-PQ208 sa pamamagitan ng Microsemi at M1AFS250-1PQ208 sa pamamagitan ng Microsemi. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microsemi
M1AFS250-PQ208 - Fusion Mixed-Signal FPGA 250K Gates | Microsemi
M1AFS250-PQ208 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | M1AFS250-PQ208 | M1AFS250-1PQ208 |
|---|---|---|
| Brand | Microsemi | Microsemi |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Logic Gates | 250000 gates | — |
| Fabric Cells / VersaTiles | 6144 cells | — |
| Number of I/O | 93 | — |
| User Flash Memory | 36864 bits | — |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V to 1.575 V) |
| Process Technology | 130 nm flash CMOS | — |
| Configuration Memory | Flash-based, on-chip (nonvolatile) | On-chip flash (single-chip, secure) |
| Security | 128-bit flash lock, AES decryption | — |
| Packhaging | 208-Pin PQFP / BFQFP | 208-BFQFP (PQ208), square |
| Terminal Pitch | 0.5 mm | 0.5 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Analog Blocks | Configurable analog (ADC inputs, monitoring) per Fusion family | — |
| Clock Management | On-chip PLL / clock conditioning circuitry | On-chip clock generation and management circuitry |
| Power-Up Behavior | Functional immediately at power-up (no external boot device) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-Compliant |
| Max Frequency Reference | 1098.9 MHz (family listing per Kynix) | — |
| Number of System Gates | — | 250000 |
| Programmable I/O | — | 93 |
| Total RAM Bits | — | 36864 |
| Technology | — | 130 nm CMOS, flash-based |
| Terminal Form | — | Gull Wing |
| Family | — | Fusion (M1) Mixed-Signal FPGA |
| Integrated Analog Blocks | — | Yes (configurable analog) |
| Lead Free Status | — | Contains Lead |
| Max Fabric Frequency | — | [DATA_NEEDED: maximum fabric frequency] |