MC9S12C64MFUE vs MC9S12C64CFUE Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng MC9S12C64MFUE sa pamamagitan ng NXP Semiconductors at MC9S12C64CFUE sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | MC9S12C64MFUE | MC9S12C64CFUE |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | NRND | NRND |
| Core | HCS12 (CPU12) | HCS12 (CPU12) |
| Width ng Data Bus | 16 bit | 16 bit |
| Program Memory Size | 64 KB Flash | 64 KB Flash |
| RAM Size | 4 KB | 4 KB |
| EEPROM Size | 1 KB | — |
| Maximum Clock Speed | 50 MHz (internal); 25 MHz bus | — |
| Volte ng Pagbibigay | 2.97 V to 5.5 V | 2.97 V to 5.5 V |
| I/O Pins | 31 | 31 |
| Package Type | 80-pin LQFP (QFP-80) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 C to +125 C | -40 C to +85 C |
| On-chip Voltage Regulator | Yes (bandgap-based Vreg) | Bandgap-based Vreg (internal VDD) |
| PLL | Yes | — |
| Communication Interfaces | SCI, SPI, IIC, CAN | — |
| Debug Interface | BDM (Background Debug Mode) | BDM (single-wire Background Debug Mode) |
| Tindminan RoHS | Compliant | Compliant |
| Maksimum na Taktiko ng Oras | — | 50 MHz (PLL, internal bus) |
| Base Clock Frequency | — | 25 MHz |
| ADC | — | 8-channel, 10-bit |
| CAN | — | 1 x CAN 2.0 A/B (1 Mbit/s) |
| UART (SCI) | — | 2 |
| SPI | — | 1 |
| Timers | — | ECT 16-bit, 8-bit modulo, PWM, PIT |
| Packhaging | — | 80-pin LQFP (QFP 80), 14x14 mm |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |