RTAX250SL-1LG624E vs RTAX250SL-1CG624E Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng RTAX250SL-1LG624E sa pamamagitan ng Microchip Technology at RTAX250SL-1CG624E sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
RTAX250SL-1LG624E - 250K Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1LG624E ✓ NakahandaMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ NakahandaPagsanggunian na paghahambing
| Parametro | RTAX250SL-1LG624E | RTAX250SL-1CG624E |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | RTAX-SL Radiation-Tolerant FPGA | — |
| Equivalent System Gates | 250000 | 250,000 gates |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Logic Cells | 4224 | 4224 |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Speed Grade | -1 (fastest) | — |
| Packhaging | 624-Pin LGA (LG624), ceramic | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Temperature na Operasyon | -55C to +125C | -55C to +125C |
| Configuration Type | One-time programmable, live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide routable reset | — |
| Packaging Option | Box | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (ceramic column grid array) |
| Target Market | Space flight systems | — |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| Radiation Tolerance | — | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |