XC3090L-100PC84C vs XC3090L-8PCG84C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng XC3090L-100PC84C sa pamamagitan ng Xilinx at XC3090L-8PCG84C sa pamamagitan ng Xilinx. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | XC3090L-100PC84C | XC3090L-8PCG84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | XC3000 | XC3000A/L Series FPGA |
| Series | XC3090L (Low Power) | — |
| Logic Cells / CLBs | 320 Configurable Logic Blocks | 70 Configurable Logic Blocks |
| Gate Count (typical) | 5,000 to 6,000 gates | — |
| Maximum Operating Frequency | 100 MHz | — |
| Speed Grade | -100 | -8 (moderate) |
| Process Technology | CMOS, 5 micron | [DATA_NEEDED: process node] |
| Volte ng Pagbibigay | 5 V | — |
| Packhaging | 84-pin PLCC (PC84) | 84-pin PLCC (J-Lead, PCG84) |
| Package Code | PC84C | — |
| Uri ng Pagpapasok | Through-Hole / Socket (PLCC) | Surface Mount (PLCC J-Lead) |
| Temperature na Operasyon | Commercial (0C to +70C) | 0 C to +70 C (commercial 'C' suffix) |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| Configuration Method | Xilinx XACT bitstream | — |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | unknown |
| Level ng MSL | [DATA_NEEDED: msl_level] | [DATA_NEEDED: MSL rating] |
| Lead Free | [DATA_NEEDED: lead_free] | — |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| User I/O Pins | — | 70 (maximum) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Lead-Free | — | unknown |
| Programming Technology | — | SRAM-based, in-system reconfigurable |