XC3090LTM-8PC84C vs XC3090L-8PCG84C Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng XC3090LTM-8PC84C sa pamamagitan ng Xilinx at XC3090L-8PCG84C sa pamamagitan ng Xilinx. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Xilinx
XC3090L-8PCG84C XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family

XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family

XC3090L-8PCG84C ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro XC3090LTM-8PC84C XC3090L-8PCG84C
Brand Xilinx Xilinx
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family XC3000L Low Voltage Logic Cell Array XC3000A/L Series FPGA
Logic Cells / Gates ~6,000 usable gates —
Configurable Logic Blocks (CLBs) 320 —
Configuration Memory 64,160 bits (distributed SRAM) —
Configuration Method External EEPROM/EPROM/ROM/master/microprocessor mode —
Core Supply Voltage 3.0 V to 3.6 V (3.3 V typical) —
Process Technology 0.8 um CMOS SRAM-based [DATA_NEEDED: process node]
Packhaging 84-Pin Plastic Leaded Chip Carrier (PLCC, J-Lead) 84-pin PLCC (J-Lead, PCG84)
Bilang ng Pin 84 —
Uri ng Pagpapasok Surface Mount (PLCC socket-compatible) Surface Mount (PLCC J-Lead)
Speed Grade -8 (per suffix; see device decoder) -8 (moderate)
Temperature na Operasyon -40 C to +85 C (industrial, TM suffix typically commercial/industrial) 0 C to +70 C (commercial 'C' suffix)
Maximum Toggle Frequency [DATA_NEEDED: specific fmax value] —
Logic Block Delays [DATA_NEEDED: typical TBU/TPIO delay] —
I/O Standard Support TTL/CMOS 3.3 V (5 V tolerant with restrictions) —
Tindminan RoHS unknown unknown
Lead-Free unknown unknown
Programming Toolchain XACT / Foundation (legacy, EOL software) —
Logic Cells / CLBs — 70 Configurable Logic Blocks
Gate Count — 6,400 gates (typical)
Configuration Program Store — 64,160 bits
User I/O Pins — 70 (maximum)
Supply Voltage (VCC) — 3.0 V to 3.6 V (low-voltage 'L' variant)
Configuration Modes — Serial master/slave, parallel master/slave, peripheral mode
JTAG / Boundary Scan — IEEE 1149.1 compliant
Configuration Clock Range — [DATA_NEEDED: CCLK frequency range]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Technology — SRAM-based, in-system reconfigurable

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