ADF4372BCCZ - 62.5MHz-16GHz Integer-N PLL with Integrated VCO | Analog Devices
MPN: ADF4372BCCZ ✓ NakahandaADF4372BCCZ Ulas
A PLL frequency synthesizer is a closed-loop timing device: a phase-frequency detector compares a divided output against a stable reference, and a charge pump plus loop filter converts the phase error into a tuning voltage that steers the internal VCO. When used with an external reference and an external loop filter, the ADF4372 supports both fractional-N and integer-N synthesis architectures, a hybrid approach in which a programmable fractional modulus shapes the reference ratio so the output can land on frequencies that are not integer multiples of the reference.
Key features include a 62.5 MHz to 16 GHz total tuning range in a single monolithic part, double-buffered registers for FRAC1, MOD2, FRAC2, reference doubler, reference divide-by-2, R counter, and charge pump current settings, and a low-noise charge pump that drives the external loop filter. Because the reference divider, fractional modulus, and charge pump current are all double buffered, the synthesizer can be retuned without dropping out of lock, which is essential for fast frequency switching in test equipment and microwave front ends.
The device accepts an external reference frequency and requires an external loop filter, giving the designer freedom to trade phase noise against lock time and reference multiplication ratio. Its architecture deliberately separates the reference path from the RF path: the R counter sets the reference division, while the N counter and fractional fields set the feedback division, so the synthesizer can be configured without changing the reference source.
Typical applications include 5G and microwave radio base-station and backhaul frequency generation, radar and electronic warfare test benches, wideband test and measurement instrumentation, satellite and VSAT up-converters, and microwave front-end local oscillator synthesis for phased-array receivers and 5G mmWave radio units.
When designing with the ADF4372BCCZ, budget loop-filter components against the target lock time and phase-noise mask, and keep the VCO supply and reference paths on separate, well-decoupled rails because supply ripple at the VCO supply pin directly multiplies into phase noise. The exposed pad must be soldered to a solid ground plane for both thermal and return-path reasons.
This page consolidates the manufacturer specifications, package and pin details, drop-in alternatives, and hands-on design guidance for the ADF4372BCCZ into one engineering reference, adding the comparison and integration detail that the datasheet leaves to the reader.
Mga alternatibo na pwedeng ilagay na ADF4372BCCZ — parehas na package, pin-to-pin na katugmang. Hindi kasama ang mga bahagi ng iba't-ibang package na nangangailangan ng pagpapaayos ng PCB.
Variante sa Seri na ito
Katulad na modelo sa serye na katugma sa pagpasok ADF4372BCCZ (parehas na form factor at footprint) — pagkakaiba sa Package, Device Type, Loop Filter, Maximum RF Output Frequency, Minimum RF Output Frequency.
ADF4371BCCZ
✅ Drop-InMagkontak para sa presyo
Tingnan ang Datasheet →ADF4377BCCZ-U3
✅ Drop-In📋 Alternatibo na Reference (hindi sa katalogo)
ADF5610BCCZ
✅ Drop-In ⚠️ Mga Talaan Hindi NaiwerikmoMagkontak para sa presyo
Tingnan ang Datasheet →ADF4372BCCZ Mga Spesipikasyon
| Device Type | Integer-N / Fractional-N PLL frequency synthesizer with integrated VCO |
| Output Frequency Range | 62.5 MHz to 16 GHz |
| VCO Fundamental Frequency Range | 4000 MHz to 8000 MHz |
| Frequency Multiplier Output Range | 8 GHz to 16 GHz (RF16x) |
| Output Divide Ratios | 1, 2, 4, 8, 16, 32, 64 |
| Lowest Divide Output | 62.5 MHz at RF8x |
| Auxiliary Output | RFAUX8x duplicates the RF8x output |
| PLL Architecture | Integer-N and fractional-N with external loop filter |
| Loop Filter | External (user selected) |
| Reference Input | External reference frequency required |
| Double-Buffered Registers | FRAC1, MOD2, FRAC2, reference doubler, RDIV2, R counter, charge pump current |
| Number of Channels | 1 |
| Packhaging | 48-lead TFLGA with exposed pad (CCZ) |
| Uri ng Pagpapasok | Surface Mount |
| Tindminan RoHS | unknown |
| REACH Status | unknown |
| AEC-Q100 Qualification | not_applicable |
Gabay sa Pin Configuration ng ADF4372BCCZ 48-lead tflga with exposed pad (ccz)
Pin configuration para sa ADF4372BCCZ (48-lead tflga with exposed pad (ccz) package). Ang pagnunumero ng pin, mga function, at connection diagram ay tinukoy sa datasheet ng manufacturer. Sumangguni dito para sa eksaktong footprint at mga alituntunin sa soldering.
Wala ng detalyadong pinout data na magagamit para sa ADF4372BCCZ.
Sumangguni sa datasheet para sa buong pin configuration.
Tipikal na mga Gamit
ADF4372BCCZ ay nararapat para sa 6 aplikasyons: Microwave Local Oscillator for 5G mmWave Radio, Wideband Test and Measurement Signal Source, Radar and Electronic Warfare Test Bench, Satellite and VSAT Up-Converter LO, Phased-Array Radar Front End, Microwave Communication and Point-to-Point Link.
Microwave Local Oscillator for 5G mmWave Radio
The ADF4372BCCZ fits a 5G mmWave transceiver local oscillator because the integrated VCO covers a 4000 MHz to 8000 MHz fundamental and the RF16x multiplier path extends generation to 16 GHz, while the divide chain brings the low end down to 62.5 MHz at RF8x. In a typical radio you would place the part on the local oscillator board, reference it from a shared low-noise reference distribution, and run an external loop filter sized for the fast frequency switching the 3GPP burst timing requires. The double-buffered FRAC1, MOD2, FRAC2, reference doubler, RDIV2, R counter, and charge pump current registers mean the synthesizer can be retuned between channels without dropping out of lock, which is the difference between a usable LO and a settling-time bottleneck in a handover scenario.
Inirekomenda
Wideband Test and Measurement Signal Source
A wideband signal generator covering 62.5 MHz to 16 GHz is exactly the span the ADF4372BCCZ provides from one device, and that removes the switch matrix that a multi-VCO lab source would otherwise need. The synthesizer is set up as an integer-N or fractional-N PLL with an external loop filter and an external reference, so the instrument designer chooses the reference multiplication ratio and filter bandwidth to hit the phase-noise and settling-time targets of the test specification. Because the fractional modulus fields are double buffered, a sweep or a stepped-list measurement can change the output frequency without an unlock event, which keeps amplitude and phase noise stable across a measurement sequence and improves test throughput.
Inirekomenda
Radar and Electronic Warfare Test Bench
Radar test benches and electronic warfare simulations need accurate, repeatable microwave excitation across a wide band, and the ADF4372BCCZ supplies 62.5 MHz to 16 GHz from an integrated VCO with a programmable divide chain and multiplier path. The external loop filter is the key freedom in this application: by selecting charge pump current, R counter, and feedback division, the designer can trade phase noise against lock time to hit a stimulus waveform that settles inside a radar repetition interval. The RFAUX8x output duplicates the RF8x output, which allows one synthesizer to feed two parallel receiver channels and keep them phase coherent without a second PLL and its matching reference distribution.
Inirekomenda
Satellite and VSAT Up-Converter LO
Satellite and VSAT up-converters need a low-phase-noise local oscillator at microwave frequencies with enough tuning range to cover multiple transponder bands. The ADF4372BCCZ supplies that from an integrated VCO fundamental of 4000 MHz to 8000 MHz, with multiplication to 16 GHz for higher-frequency plans and division down to 62.5 MHz where a low-frequency LO feed is more convenient. Because the reference divider, fractional modulus, and charge pump current are all double buffered, the synthesizer can hop between transponder channels under a fast hopping scheme without re-locking, and the whole assembly stays small enough to sit in a compact outdoor or flyaway terminal where board area is at a premium.
Inirekomenda
Phased-Array Radar Front End
Phased-array radar front ends need many coherent excitation or reference signals with accurate relative phase, and the ADF4372BCCZ provides a single wideband source that can be split and distributed rather than replicated. Because the entire 62.5 MHz to 16 GHz span comes from one integrated VCO, a beamformer can run multiple sub-bands from the same part family and preserve coherence through a common reference distribution network. The double-buffered FRAC1, MOD2, and FRAC2 registers allow the synthesizer to retune between waveforms in a frequency-agile radar sequence without an unlock event, while the RFAUX8x output provides a duplicated path for a parallel calibration channel.
Inirekomenda
Microwave Communication and Point-to-Point Link
Microwave backhaul and point-to-point radio links operate in frequency bands where a stable, low-noise local oscillator is the determining factor in modulation quality. The ADF4372BCCZ supports the required wideband coverage from 62.5 MHz to 16 GHz with an integer-N or fractional-N feedback architecture, letting the link designer land precisely on an assigned channel with a fractional modulus rather than changing the reference. The external loop filter gives direct control of the phase-noise skirt, which matters when the transmitted constellation must remain clean at high EVM, and the small 48-lead TFLGA footprint with exposed pad keeps the synthesizer section compact in outdoor radio units.
Inirekomenda
Buod ng mga Inirekomendang Produkto
Impormasyon ng Talumpati sa Engineering for ADF4372BCCZ — ikabit, gabay sa disenyo, at impormasyon ng pagsunod sa kautusan.
Paunawang Hanapin
Ikabit sa Mga Alternatibo
| Parametro | Ito ang Producto | ADF4371BCCZ | ADF4377BCCZ-U3 | ADF5610BCCZ |
|---|---|---|---|---|
| Package | 48-lead TFLGA with exposed pad (CCZ) | 48-lead TFLGA with exposed pad (CCZ) - same | 48-lead TFLGA with exposed pad (CCZ) - same | 48-lead TFLGA with exposed pad (CCZ) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Device Category | Clock Generators, PLLs, Frequency Synthesizers | Clock Generators, PLLs, Frequency Synthesizers | Clock Generators, PLLs, Frequency Synthesizers | Clock Generators, PLLs, Frequency Synthesizers |
Pangunahing mga Pagkakaiba
- Widest integrated coverage in one synthesizer (kumpara saADF4371BCCZ)
- Lock-preserving retuning via double-buffered fractional and charge pump registers (kumpara saADF4377BCCZ-U3)
- RFAUX8x duplicated output for coherent multi-channel use (kumpara saADF5610BCCZ)
- Honest trade-off versus a discrete VCO approach (kumpara saDiscrete VCO plus divider chain)
Talaan ng Disenyo
Estimated: the ADF4372BCCZ integrates the VCO, so its core supply rejection directly sets the output phase-noise floor. Treat the VCO supply rail as the noisiest node on the board - place a ferrite bead or RC isolation between the switching supply and the VCO supply pin, and add the datasheet-recommended local ceramic decoupling at the supply pins. Never route the reference or charge pump rails over the VCO supply return path, because shared return impedance converts supply ripple into tuning voltage noise.
Place the external loop filter components close to the charge pump and N-counter pins and keep those traces short, since parasitic inductance in the filter loop adds phase shift and can make the loop unstable or shift the damping you designed for. Use the pin-description table in the manufacturer data sheet to assign tracks, route the RF outputs on controlled impedance with a continuous ground reference, and connect the exposed pad to a solid, uninterrupted ground plane so the pad can act as both the thermal path and the RF return.
A frequent bring-up mistake is assuming the on-chip dividers can be selected freely across the whole band. The ADF4372BCC2 divide chain of 1, 2, 4, 8, 16, 32, or 64 operates from the VCO fundamental, so the RF8x output can reach 62.5 MHz while RF16x multiplication only produces 8 GHz to 16 GHz. Program the output path and the N counter together, and re-run the loop filter simulation with the actual reference division ratio whenever the reference doubler or RDIV2 setting changes.
The double-buffered fractional and charge pump registers allow retuning without unlocking, but they only help if the SPI writes are sequenced correctly. Issue the register update after the integer and fractional fields are staged, and keep SPI clock edges away from the reference and VCO supply routing. When driving a long reference cable into the device, terminate it properly and decouple close to the reference input pin so reference spurs do not dominate the close-in phase-noise spectrum.
Impormasyon ng Pagsunod sa Kautusan
RoHS and REACH status are compared for this part against family members in published component comparison listings, but the definitive compliance declarations for the ADF4372BCCZ should be confirmed on the manufacturer product page and the current material declaration before release.
