EP1M350F780C8 vs EP1M350F780C6N Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP1M350F780C8 tarafından Altera ve EP1M350F780C6N tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Son Satın AlmaÖzellik Karşılaştırması
| Parametre | EP1M350F780C8 | EP1M350F780C6N |
|---|---|---|
| Marka | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | Son Alış Zamanı |
| Device Family | Altera APEX Mercury (EP1M) | — |
| Typical Gates | 350,000 | — |
| Maximum Logic Elements (LEs) | 12,160 | — |
| Embedded RAM Blocks | 4 dual-port RAM blocks | — |
| Paket | 780-ball FineLine BGA | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Speed Grade | C8 (commercial, speed bin 8) | — |
| İşletim Sıcaklığı | 0C to +85C (commercial) | 0 C to 85 C |
| Supply Voltage (Core) | [DATA_NEEDED: core Vcc] | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards) | — |
| Global Clock Networks | 8 | — |
| Configuration Interface | IEEE 1532 / passive serial / JTAG | JTAG (IEEE 1149.1) / passive serial |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| RoHS Durumu | unknown (legacy device) | [DATA_NEEDED: rohs_status] |
| Montaj Türü | Surface Mount (BGA) | — |
| MSL Seviyesi | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: msl_level] |
| Family | — | Mercury (EP1M350) |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |