EPC16UI88 vs EPC16UC88 Karşılaştırma
Ayrıntılı yan yana karşılaştırma EPC16UI88 tarafından Altera ve EPC16UC88 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EPC16UI88 | EPC16UC88 |
|---|---|---|
| Marka | Altera | Altera |
| Kategori | FPGA & CPLD | Memory ICs |
| Yaşam Döngüsü Durumu | NRND | Unknown |
| Memory Density | 16 Mb (2 MB) | — |
| Configuration Interface | Altera Passive Serial / Passive Parallel (Sync & Async) / JTAG | — |
| Core Supply Voltage | 3.3 V | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Maximum Configuration Clock | 100 MHz | — |
| Cascading Support | Multi-device configuration chains | — |
| Supported FPGA Families | Altera Cyclone II/III/IV, Stratix II/III, APEX II | — |
| Paket | 88-ball UBGA (Ultra FineLine BGA), 11x8 mm | 88-UBGA (11x8) |
| Montaj Türü | Surface Mount | Surface mount |
| İşletim Sıcaklığı | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature] |
| Standby Current | [DATA_NEEDED: standby current] | — |
| Active Configuration Current | [DATA_NEEDED: active configuration current] | — |
| Programming Cycles | [DATA_NEEDED: programming endurance cycles] | — |
| RoHS Durumu | Compliant | [DATA_NEEDED: RoHS status] |
| Configuration Time | [DATA_NEEDED: configuration time for typical 16 Mb bitstream] | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Besleme Gerilimi | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |