RTAX2000S-1CG624PROTO vs RTAX2000S-CG624PROTO موازنہ
تفصیلی ساتھ ساتھ موازنہ از RTAX2000S-1CG624PROTO بذریعہ Microchip Technology اور RTAX2000S-CG624PROTO بذریعہ Microchip Technology. اہم خصوصیات، برقی پیرامیٹرز، پیکیجنگ، لائف سائیکل اسٹیٹس، قیمتوں اور دستیابی کا موازنہ کریں تاکہ آپ کی ڈیزائن ضروریات کے لیے بہترین کمپوننٹ کا تعین ہو سکے۔
Microchip Technology
RTAX2000S-1CG624PROTO - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CG624PROTO ✓ فعالMicrochip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ فعالخصوصیات کا موازنہ
| پیرامیٹر | RTAX2000S-1CG624PROTO | RTAX2000S-CG624PROTO |
|---|---|---|
| برانڈ | Microchip Technology | Microchip Technology |
| زمرہ | FPGA & CPLD | FPGA & CPLD |
| لائف سائیکل کی حالت | فعال | فعال |
| Equivalent System Gates | 2000000 | — |
| Logic Cells | 32256 | — |
| Configurable Logic Blocks (CLBs) | 21504 | — |
| Embedded Memory | 540 kbits (family max, with optional EDAC) | Embedded SRAM blocks (FIFO / dual-port capable) |
| User I/Os (family max) | 684 | — |
| Total Ionizing Dose (functional) | 300 krad (Si) | — |
| Total Ionizing Dose (parametric) | 200 krad (Si) | — |
| SEU Rate | Less than 1E-10 errors per bit-day | — |
| Maximum System Frequency | 350 MHz (family performance) | — |
| Technology | CMOS antifuse (one-time programmable) | — |
| Speed Grade | -1 | — |
| پیکیج | CCGA-624 (CG624 ceramic column grid array) | CCGA-624 (ceramic column grid array, 624 balls) |
| Configuration | Live at power-up (nonvolatile antifuse) | Live at power-up (non-volatile antifuse) |
| Qualification Flow | PROTO (engineering prototype) | — |
| ماؤنٹنگ ٹائپ | Surface Mount | Surface Mount |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S Radiation-Tolerant FPGA |
| RoHS اسٹیٹس | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| آپریٹنگ درجہ حرارت | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| System Gates | — | 2,000,000 |
| Logic Cells (R-cells) | — | 21,504 |
| D-Flip-Flops (Registers) | — | 32,256 |
| Logic Architecture | — | CMOS antifuse (OTP), SEU-hardened |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU rate < 10^-10 errors/bit-day (per family datasheet) |
| Prototyping Variant | — | Yes (PROTO suffix) |
| I/O Standards | — | Single-ended and differential (P/N pin pairs) |
| Design Software | — | Microsemi/Microchip Libero SoC |
| سپلائی وولٹیج | — | [DATA_NEEDED: core and I/O supply voltage] |
| Total Ionizing Dose (TID) | — | [DATA_NEEDED: TID rating in krad(Si)] |
| Maximum I/O Count (624-ball pkg) | — | [DATA_NEEDED: user I/O count] |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |