ASM58048 - 48-Lane 16-Port PCIe 4.0 Switch | ASMedia Technology
MPN: ASM58048 ✓ Hoạt độngASM58048 Tóm tắt
A PCIe packet switch is a switching fabric device that sits in the PCI Express hierarchy between a host root complex and multiple endpoints. It performs store-and-forward or cut-through packet routing of TLPs (Transaction Layer Packets), enabling one upstream port to fan out to several downstream ports. In the system hierarchy, the device spans PCIe switch -> interconnect fabric -> host interface -> high-speed serial interface -> semiconductor.
Key characteristics include 48 lanes of PCIe connectivity and 16 configurable ports, giving system architects flexible bifurcation options for connecting multiple NVMe SSDs, GPUs, or network adapters to a limited number of host CPU lanes. ASMedia states that full compatibility and performance comparable to international competitors were design targets, and that the device's own fully verified PHY technology underpins the silicon.
The architecture leverages ASMedia's in-house PHY IP, and the follow-on PCIe Gen5 product with independently verified PHY is nearing design finalization, indicating the ASM58048 targets the PCIe Gen4 class of interconnect workloads.
Typical applications include NAS high-speed cache acceleration - per ASMedia's CES 2026 announcement, the ASM58048 enables multiple high-speed NVMe SSDs to be connected at the NAS front end forming a high-speed cache tier for AI data preprocessing - plus AI workstation GPU expansion, server storage backplanes, and add-in-card fan-out designs.
When designing with this device, confirm lane allocation and bifurcation settings against your board's power and reference-clock topology, and validate link training across all 16 ports in system-level bring-up.
This page synthesizes PCI-SIG registration data, manufacturer press releases, and drop-in replacement guidance not found in distributor listings.
Bộ thay thế dễ dàng lắp đặt cho ASM58048 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Không có bộ thay thế dễ dàng lắp đặt sẵn có cho sản phẩm này.
Yêu cầu các bộ thay thếASM58048 Tỷ lệ tối đa & tính chất điện
| Chức năng | 48 Lane, 16 Port PCIe Switch |
| Total PCIe Lanes | 48 lanes |
| Total Ports | 16 ports |
| Interface Standard | PCI Express Packet Switch |
| Manufacturer | ASMedia Technology Inc. |
| PCI-SIG Registered Identifier | ASM58048 |
| Sampling Availability | Q3 2025 (per ASMedia COMPUTEX 2025 announcement) |
| Product Family Roadmap | ASMedia PCIe packet switch line, 3 to 80 lanes, all PCIe generations |
| PHY Technology | ASMedia in-house fully verified PHY |
| Kiểu lắp đặt | Surface Mount |
Hướng dẫn cấu hình chân ASM58048 standard
Cấu hình chân cho ASM58048 (standard gói). Số thứ tự chân, chức năng và sơ đồ kết nối được xác định trong tài liệu thông số kỹ thuật của nhà sản xuất. Tham khảo nó để biết footprint và hướng dẫn hàn chính xác.
Không có dữ liệu chân cụ thể sẵn có cho ASM58048.
Tham khảo: tài liệu kỹ thuật cho cấu hình chân đầy đủ.
Ứng dụng tiêu biểu
ASM58048 phù hợp cho 6 Áp dụngs: NAS High-Speed Cache Acceleration, AI Workstation GPU Fan-Out, Server NVMe Storage Backplane, AI Data Preprocessing Pipelines, Add-In-Card Expansion / Fan-Out Riser, Industrial and Edge Compute Gateways.
NAS High-Speed Cache Acceleration
ASMedia's CES 2026 announcement positions the ASM58048 as the enabling switch for NAS high-speed cache tiers. In this topology, the ASM58048 fans out from the NAS controller's upstream PCIe interface to multiple high-speed NVMe SSDs at the storage front end, forming a cache tier dedicated to AI data preprocessing and frequent-access workloads. With 48 lanes across 16 ports, the switch can offer x4 links to up to 12 NVMe drives simultaneously, keeping sequential throughput at the drive's full lane rate while reserving downstream ports for capacity tiers. Compared with drive-multiplexing via port multipliers, a PCIe packet switch preserves each SSD's dedicated bandwidth, which directly reduces cache-miss latency during AI training data ingestion.
Được đề xuất
AI Workstation GPU Fan-Out
The ASM58048's 48-lane capacity suits AI workstations where a host CPU provides limited PCIe lanes but multiple accelerators or capture cards must be connected. Placed between the CPU's root port and several x8 GPU slots, the switch allocates lanes via hardware or firmware-configured bifurcation, preserving full-width links where bandwidth matters. ASMedia demonstrated the part at COMPUTEX 2025 specifically in AI application contexts, and its packet-switch fabric maintains peer-to-peer DMA paths between endpoints, which benefits multi-GPU gradient synchronization by reducing host round-trips. Designers should budget board space for the switch package, verify reference clock distribution across all 16 ports, and validate link training under worst-case temperature conditions.
Được đề xuất
Server NVMe Storage Backplane
In 1U/2U server storage designs, the ASM58048 converts a narrow upstream root-complex link into many downstream NVMe drive slots. A typical configuration routes an x16 upstream link into six to twelve x4 downstream slots for U.2/M.2 carriers, with the remaining ports handling management, LED control endpoints, or fabric expansion. Because the switch presents standard PCIe TLP routing with no protocol translation, hot-plug and surprise-removal behavior follows native PCIe semantics, simplifying OS driver support. Signal integrity across a backplane demands attention to lane length matching and AC coupling; the switch's own verified PHY, per ASMedia, is the core technology enabler for full compatibility with standard PCIe topologies.
Được đề xuất
AI Data Preprocessing Pipelines
ASMedia's CES 2026 release explicitly ties the ASM58048 to AI data preprocessing and frequent-access workloads. In such pipelines, datasets staged on NVMe media must be streamed to accelerator memory with minimal jitter; a PCIe packet switch provides deterministic per-lane bandwidth without USB or SAS translation overhead. Deploying the ASM58048 at the storage front end lets multiple SSDs operate in parallel at full PCIe lane rates, raising aggregate read throughput proportionally to drive count until the upstream link saturates. Engineers should size the upstream link (x8 or x16) to avoid becoming the bottleneck, and monitor switch-side congestion during mixed read/write pre-processing jobs.
Được đề xuất
Add-In-Card Expansion / Fan-Out Riser
The ASM58048 fits riser and expansion-card designs where a single host slot must serve several endpoints. A riser card carrying the ASM58048 converts one x16 host slot into multiple downstream x4/x8 slots on the card itself, useful in dense enclosures, industrial PCs, and edge AI boxes. Because the switch handles TLP routing internally, downstream devices enumerate transparently with no special host drivers in most OS environments. Thermal design is the main constraint: switching 48 lanes of high-speed serial traffic dissipates meaningful power in a confined card footprint, so designers should plan airflow and copper pours per the NDA datasheet's thermal guidance.
Được đề xuất
Industrial and Edge Compute Gateways
Edge AI gateways benefit from the ASM58048's ability to attach heterogeneous endpoints - NVMe storage, FPGA accelerators, and network interface cards - to a single upstream host link. With 16 ports, the switch supports a mixed endpoint population while PCIe's native isochronous behavior preserves latency-sensitive traffic classes. Industrial deployments additionally value supply-chain diversification: ASMedia's entry gives designers a switch fabric source outside the traditional Broadcom/Microchip duopoly, which mitigates allocation risk. For ruggedized designs, confirm the operating temperature range from the NDA datasheet before committing, as extended-temperature qualification for this newly sampled part is not publicly documented as of 2026-10-19.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ASM58048 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | PM40100-B0EG | PEX88096-B3 |
|---|---|---|---|
| Brand | ASMedia Technology Inc. | Microchip Technology | Broadcom |
| PCIe Lanes | 48 lanes | 100 lanes | 96 lanes |
| Production Status | Sampling Q3 2025 / ramping | Volume production | Volume production |
| Drop-In Compatible | - | No - different package and pinout | No - different package and pinout |
Bảo phân biệt quan trọng
- Supply-chain diversification in the 48-lane switch class (vsPM40100-B0EG)
- In-house verified PHY technology (vsPEX88096-B3)
- Port density per lane (vsPM40100-B0EG)
Ghi chú thiết kế
A 48-lane, 16-port PCIe switch places demanding requirements on reference clock and lane routing. Distribute a clean 100 MHz reference clock (separate HCSL outputs or a PCIe clock buffer) to the switch and all downstream endpoints, and keep lane length mismatch within PCIe-spec skew limits. For backplane topologies, budget for AC coupling capacitors near the receiver and evaluate whether retimers are needed on lanes longer than the NDA datasheet's reach guidance. Validate link training across all 16 ports under worst-case temperature in system bring-up.
Switching 48 high-speed serial lanes at Gen4-class data rates dissipates substantial power in a compact BGA footprint. Estimated: power dissipation is not publicly published, so obtain the NDA datasheet's power tables before designing the VRM. Plan core and PHY rails independently, sequence rails per the datasheet's power-up ordering, and provision decoupling per ASMedia's reference design. Because no public thermal resistance figure exists as of 2026-10-19, perform a junction-temperature estimate only after official power and theta-JA figures are obtained.
Do not confuse the ASM58048 with unrelated parts sharing the numeric string "58048" - notably the Microsemi/Microchip 58048 RF power transistor and the Molex 5.00mm connector series. Search results and legacy distributor listings frequently mix these. Also note the ASM58048 began sampling only in Q3 2025; assume early-production firmware/configuration-tool maturity risk, secure the NDA documentation early, and lock your PCB layout only after receiving the confirmed package ballout.
Thông tin tuân thủ
Compliance data not published in verified web data as of 2026-10-19; confirm via ASMedia product brief under NDA.