CS5532-BSZ - 24-Bit Sigma-Delta ADC with PGIA | Cirrus Logic
MPN: CS5532-BSZ ✓ Hoạt độngCS5532-BSZ Tóm tắt
A delta-sigma ADC is a type of analog-to-digital converter that oversamples the input signal and uses noise-shaping (charge-balanced sigma-delta modulation) followed by digital decimation filtering to achieve very high resolution - here 24 bits - far exceeding what successive-approximation converters offer. Within the signal-chain hierarchy, this device belongs to the data acquisition category: sensor -> instrumentation amplifier -> delta-sigma ADC -> digital interface, and the CS5532 integrates the amplifier stage directly on-chip.
Key features include the on-chip PGIA with programmable gains from 1x to 64x, which lets microvolt-level bridge or thermocouple signals be amplified and digitized in a single integrated stage; a low-noise analog front end optimized for low-level unipolar or bipolar signals; a simple 3-wire serial (SPI-compatible) digital interface; and calibration options (system and self-calibration) that remove offset and gain error without external trimming.
Architecturally, the converter uses charge-balanced delta-sigma techniques combined with a linear-phase digital decimation filter. The high oversampling ratio pushes quantization noise out of band, while the internal filter reconstructs high-resolution output words, enabling direct connection of load cells, RTDs, and thermocouples with minimal external circuitry.
Typical applications include weigh scales and load-cell measurement, industrial process control loops, scientific instrumentation, and medical equipment such as patient-monitoring front ends - all domains where microvolt sensitivity and linearity matter more than raw speed.
When designing with the CS5532-BSZ, provide a clean, low-noise reference voltage on VREF+, keep the analog and digital ground returns star-connected, and allow for periodic system calibration in firmware to null drift over temperature.
This page adds value beyond the manufacturer datasheet by consolidating drop-in alternatives, distributor pricing context, and practical layout and design guidance in one place.
Bộ thay thế dễ dàng lắp đặt cho CS5532-BSZ — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với CS5532-BSZ (cùng hình factor và footprint) — khác nhau ở Number of Input Channels, Package, Interface, Calibration, Converter Type.
CS5534-BSZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CS5534-ASZR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CS5533-ASZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CS5531-ASZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CS5532-ASZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CS5532-BSZ Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 24 bit |
| Converter Type | Delta-Sigma (charge-balance) |
| Number of Input Channels | 2 (differential, multiplexed) |
| Input Type | Differential |
| Integrated PGIA Gains | 1x to 64x (programmable) |
| Maximum Output Word Rate | 3.84 kSPS |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3 V to 5 V |
| Giao diện | 3-wire serial (SPI-compatible) |
| Calibration | Self and system calibration |
| Family | CS5531/32/33/34 |
| Hộp | 20-SSOP |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
| Typical Applications | Weigh scale, process control, scientific, medical |
Cấu hình chân CS5532-BSZ
| Chân 1 | XIN — Crystal oscillator input (clock source) |
| Chân 2 | XOUT — Crystal oscillator output |
| Chân 3 | /CS — Chip select (active low, serial interface) |
| Chân 4 | SDI — Serial data input |
| Chân 5 | SDO — Serial data output |
| Chân 6 | SCLK — Serial clock input |
| Chân 7 | A0 — Address / configuration input |
| Chân 8 | /PDW — Power-down (active low) |
| Chân 9 | DGND — Digital ground |
| Chân 10 | VD+ — Digital supply (3 V to 5 V) |
| Chân 11 | VA- — Negative analog supply / ground reference |
| Chân 12 | AGND — Analog ground |
| Chân 13 | AIN1- — Differential channel 1 inverting input |
| Chân 14 | AIN1+ — Differential channel 1 non-inverting input |
| Chân 15 | AIN2- — Differential channel 2 inverting input |
| Chân 16 | AIN2+ — Differential channel 2 non-inverting input |
| Chân 17 | VREF- — Reference voltage negative input |
| Chân 18 | VREF+ — Reference voltage positive input |
| Chân 19 | VA+ — Analog supply (5 V) |
| Chân 20 | INT — Interrupt / conversion-ready output |
Ứng dụng tiêu biểu
CS5532-BSZ phù hợp cho 6 Áp dụngs: Weigh Scales and Load-Cell Measurement, Industrial Process Control, Scientific Instrumentation, Medical Patient Monitoring, Temperature Measurement (Thermocouple / RTD), Data Acquisition Systems and Panel Meters.
Weigh Scales and Load-Cell Measurement
The CS5532-BSZ fits weigh-scale front ends because load cells produce only a few millivolts full scale, and the on-chip PGIA with gains up to 64x amplifies these microvolt-level signals before 24-bit digitization, all in one 20-SSOP package. Placed directly at the load-cell output with the bridge excited from a clean VREF+ supply, the charge-balance delta-sigma core averages out noise at the 3.84 kSPS maximum rate, and firmware-driven system calibration removes offset and gain drift from the bridge and cabling. Unlike a discrete amplifier-plus-ADC chain, the integrated PGIA avoids external op-amp offset and resistor-matching errors, improving long-term scale accuracy. Count-per-unit cost is reduced because filtering, amplification, and conversion are all integrated.
Được đề xuất
Industrial Process Control
In industrial process loops, transmitters and bridge sensors deliver low-level signals riding on significant common-mode voltage, and the CS5532-BSZ addresses this with a differential PGIA input and 24-bit charge-balance conversion optimized for low-level unipolar or bipolar signals. The two multiplexed channels let one ADC monitor a primary process variable and a reference or secondary channel, reducing component count on dense I/O cards. Self and system calibration performed at power-up or periodically compensates for offset and gain drift over wide plant temperature ranges. The 3-wire serial interface connects directly to standard PLC microcontrollers, and the 3-5 V digital supply eases interface to both legacy 5 V and modern 3.3 V logic on the control board.
Được đề xuất
Scientific Instrumentation
Laboratory instruments measuring low-level sensor outputs - photodiode transimpedance stages, precision bridges, and electrometer-style front ends - benefit from the CS5532-BSZ combination of a 24-bit delta-sigma converter and ultra-low-noise PGIA in a single package. The programmable gain allows one analog gain stage to cover several measurement decades, while the linear-phase digital decimation filter delivers clean high-resolution output words without additional external filtering. Because conversion is charge-balanced and oversampled, 50/60 Hz line interference can be rejected by selecting line-frequency-synchronous word rates, a classic requirement in precision bench instruments. The small 20-SSOP footprint also suits modular or portable instrumentation where board area and analog cleanliness must coexist.
Được đề xuất
Medical Patient Monitoring
Medical monitoring front ends - weight-based patient scales, infusion sensing, and physiological bridge measurements - need microvolt sensitivity with drift that firmware calibration can remove, which is exactly the CS5532-BSZ profile. According to Cirrus Logic, the CS5531/32/33/34 family is optimized for medical as well as weigh scale and process applications. The differential PGIA input rejects common-mode interference typical of hospital environments, and 24-bit resolution preserves headroom when the sensor signal spans a wide dynamic range. System calibration at each power cycle maintains accuracy without manual trimming, an important factor in serviceable medical devices. The ADC itself is a component; patient-isolation (IEC 60601) must be implemented at system level around it.
Được đề xuất
Temperature Measurement (Thermocouple / RTD)
Thermocouples generate tens of microvolts per degree Celsius, and the CS5532-BSZ's PGIA at gain settings up to 64x brings these signals into the ADC's full-scale range while the 24-bit charge-balance converter preserves sub-degree resolution. For RTD measurements, a ratiometric configuration - exciting the RTD and the ADC reference from the same current or voltage source - cancels excitation-drift error, and the differential input pair AINx+/AINx- reads the bridge directly. Firmware system calibration removes converter offset, and the multiplexed second channel can measure cold-junction compensation without a second ADC. At line-synchronous word rates, 50/60 Hz pickup from long sensor cables is inherently rejected by the digital filter, a significant benefit in industrial thermal loops.
Được đề xuất
Data Acquisition Systems and Panel Meters
General-purpose DAQ channels and precision panel meters use the CS5532-BSZ as the conversion core because it integrates amplification, filtering, and 24-bit conversion into a 20-SSOP footprint, leaving the microcontroller free for display and communication tasks. The SPI-compatible 3-wire interface works with virtually any MCU, and the register-based configuration allows word rate, gain, and calibration mode to be changed at runtime, enabling multi-range meters on a single hardware design. For retrofit of legacy 5 V systems, the 5 V analog supply matches existing rails, while the 3-5 V digital supply supports modern 3.3 V hosts. Compared with discrete PGA-plus-SAR solutions, the integrated chain reduces BOM count, calibration overhead, and board noise coupling points.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho CS5532-BSZ — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | CS5534-BSZ | CS5533-ASZ | CS5531-ASZ | CS5532-ASZ |
|---|---|---|---|---|---|
| Package | 20-SSOP | 20-SSOP - same | 20-SSOP - same | 20-SSOP - same | 20-SSOP - same |
| Brand | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic |
| Resolution | 24 bit | 24 bit | 16 bit | 16 bit | 24 bit |
| Input Channels | 2 differential | 4 differential | 2 differential | 1 differential | 2 differential |
| Converter Architecture | Delta-Sigma (charge-balance) | Delta-Sigma (charge-balance) | Delta-Sigma (charge-balance) | Delta-Sigma (charge-balance) | Delta-Sigma (charge-balance) |
| Integrated PGIA | Yes, 1x-64x | Yes, 1x-64x | Yes, 1x-64x | Yes, 1x-64x | Yes, 1x-64x |
| Interface | 3-wire serial (SPI-compatible) | 3-wire serial (SPI-compatible) | 3-wire serial (SPI-compatible) | 3-wire serial (SPI-compatible) | 3-wire serial (SPI-compatible) |
| Temperature Grade (suffix) | BS | BS | AS | AS | AS |
Bảo phân biệt quan trọng
- 24-bit resolution in the same footprint (vsCS5533-ASZ)
- Two differential channels with PGIA integrated (vsCS5531-ASZ)
- Channel-count upgrade path without redesign (vsCS5534-BSZ)
Ghi chú thiết kế
Separate analog and digital ground returns and join them at a single star point under the ADC. Place the VREF+ bypass capacitor (e.g. 10 uF ceramic plus 0.1 uF) directly at pin 18, and keep the reference trace short and guarded - reference noise appears directly in the output code at 24-bit resolution. Route the crystal traces (XIN/XOUT) short and away from the serial bus. Keep high-current digital switching (SCLK edges) away from AIN traces to prevent coupling into the PGIA input.
Feed VA+ from a low-noise linear regulator rather than a switching converter; if a buck pre-regulator is used, add an LDO post-stage. The 3-5 V digital supply may share the MCU rail, but add a series ferrite bead plus 0.1 uF at VD+ to block digital rail noise from reaching the die. Decouple AGND-referenced inputs symmetrically. Estimated: every 10 uVrms of reference noise at 2.5 V reference costs roughly 15 bits of theoretical noise-free resolution, so reference quality dominates system performance.
Do not omit periodic calibration: offset and gain drift with temperature and cannot be removed by layout alone. Perform a system calibration with the input shorted (offset) and a known full-scale signal (gain) after warm-up. Also respect PGIA gain settling - after changing gain or mux channel, discard the first conversion result as specified in the Cirrus Logic datasheet before reading valid data. Finally, do not exceed reference and input common-mode limits; the differential input range is specified relative to VREF and supply rails.
Thông tin tuân thủ
RoHS compliance indicated by the 'Z' suffix in the ordering code per standard Cirrus Logic part-numbering; other compliance statuses not stated in verified data.
