LAN8720A-CP - RMII 10/100 Ethernet PHY Transceiver | Microchip (Tape & Reel)
MPN: LAN8720A-CP ✓ Hoạt độngLAN8720A-CP Tóm tắt
An Ethernet PHY (physical layer transceiver) is the analog front-end of an Ethernet link, sitting between the RJ-45 magnetics and the MAC controller. It handles line encoding/decoding, clock recovery, link training, and signal shaping so the digital MAC can exchange frames with the network. The LAN8720A belongs to the 10/100 Fast Ethernet PHY family, positioned below Gigabit PHYs in the network interface hierarchy and above purely digital MAC-only designs that require an external analog transceiver.
Key features include an integrated 1.2V LDO regulator that can be sourced externally, very low power consumption (claimed up to 40% lower than prior Microchip PHYs), a hardware-strapped configuration for default operation, and commercial temperature grade (0 C to +85 C). The device also includes Energy-Efficient Ethernet (EEE) support and a SMI (Serial Management Interface) for PHY register access. Its 24-pin QFN footprint makes it the industry's smallest 10/100 Ethernet transceiver solution in this package size.
Architecture-wise the LAN8720A integrates a 100BASE-TX DSP-based PHY core, ADC/DAC analog blocks, line driver, HP Auto-MDIX termination switches, and a digital control block with MII/RMII muxing. The flexPWR architecture allows the core to run from 1.2V while the I/O rails stay at 1.8V/2.5V/3.3V, eliminating level shifters when paired with most modern SoCs. Power-down and energy-detect modes further reduce quiescent draw for low-power designs.
Typical applications include consumer broadband gateways, IP set-top boxes, IP phones, game consoles, industrial Ethernet nodes, and MCU-based designs such as ESP32 ethernet MAC add-on boards where the LAN8720A provides the analog PHY. It is also commonly seen in printers, networked embedded controllers, and small-office routers where space and BOM cost matter more than Gigabit throughput.
When designing with this part, select the correct external reference clock (25 MHz) source and place the device close to the RJ-45 jack magnetics to minimize EMI. Verify that the MAC supports RMII (not just MII) and route the 50 MHz RMII reference clock with controlled impedance to avoid jitter. Leave sufficient ground flooding under the exposed pad for thermal dissipation.
This page synthesizes distributor stock, drop-in alternatives, design notes and comparison data that go beyond the manufacturer datasheet, helping engineers shorten the LAN8720A-CP selection and validation cycle.
Bộ thay thế dễ dàng lắp đặt cho LAN8720A-CP — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LAN8720A-CP (cùng hình factor và footprint) — khác nhau ở Auto-Negotiation, Package.
LAN8720AI-CP-TR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN8720AI-CP
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN8742A-CZ-TR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LAN8742AI-CZ
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN8720A-CP Thông số kỹ thuật
| Chức năng | Ethernet PHY Transceiver |
| Tốc độ dữ liệu | 10/100 Mbps |
| Standards | 10BASE-T, 100BASE-TX (IEEE 802.3) |
| MAC Interface | MII, RMII |
| Điện áp cung cấp | 3.3 V (single supply, flexPWR) |
| I/O Voltages | 1.8 V / 2.5 V / 3.3 V (variable) |
| Auto-MDIX | HP Auto-MDIX supported |
| Auto-Negotiation | Yes (speed and duplex) |
| Hộp | 24-pin QFN (4x4 mm) |
| Kiểu lắp đặt | Surface Mount |
| Nhiệt độ hoạt động | 0 C to +85 C (commercial grade) |
| Reel Quantity | 4000 per reel |
| Compliance | RoHS compliant, halogen-free per IEC 61249-2-21 |
| Configuration | Hardware-strapped defaults; SMI for register access |
| Power Mode | flexPWR with Energy Detect / Power Down modes |
Cấu hình chân LAN8720A-CP
| Chân 1 | VDDCR — 1.2V core supply (internal LDO output) |
| Chân 2 | VDDIO — Variable I/O supply (1.8V/2.5V/3.3V) |
| Chân 3 | RXD0/MODE0 — RMII RX data bit 0 / strap config mode 0 |
| Chân 4 | RXD1/MODE1 — RMII RX data bit 1 / strap config mode 1 |
| Chân 5 | RXER/CRS_DV — RX error (MII) / Carrier Sense+Data Valid (RMII) |
| Chân 6 | TXEN — Transmit enable |
| Chân 7 | TXD0 — Transmit data bit 0 |
| Chân 8 | TXD1 — Transmit data bit 1 |
| Chân 9 | MDC — Management data clock (SMI) |
| Chân 10 | MDIO — Management data I/O (SMI) |
| Chân 11 | REF_CLK — 50 MHz RMII reference clock input |
| Chân 12 | nRST — Active-low hardware reset |
| Chân 13 | nINT/CLKOUT — Interrupt output / 25 MHz clock output option |
| Chân 14 | LED1/nINTSEL — LED1 drive / interrupt polarity strap |
| Chân 15 | LED2 — Link/activity LED2 drive |
| Chân 16 | GND — Ground (multiple pins, also via EP) |
| Chân 17 | VDDA — 3.3V analog supply |
| Chân 18 | TXM — Differential transmit negative |
| Chân 19 | TXP — Differential transmit positive |
| Chân 20 | RXM/RXP — Receive differential pair (magnetics side) |
| Chân 21 | RXP — Receive differential positive |
| Chân 22 | RXM — Receive differential negative |
| Chân 23 | NC — Not connected (per datasheet) |
| Chân 24 | EP — Exposed thermal pad - connect to GND |
Ứng dụng tiêu biểu
LAN8720A-CP phù hợp cho 6 Áp dụngs: ESP32 / MCU Ethernet MAC Add-on Board, Industrial Ethernet Sensor Node, IP Set-Top Box / Home Gateway, Networked Printer / Office Equipment, IP Phone / VoIP Endpoint, Game Console / Consumer Electronics.
ESP32 / MCU Ethernet MAC Add-on Board
The LAN8720A-CP is one of the most widely adopted external PHYs for ESP32 Ethernet MAC designs. The 24-QFN 4x4 mm footprint, 50 MHz RMII reference clock and 3.3V supply match the typical ESP32 reference schematic (ETH_PHY_POWER, MDC, MDIO). 10/100 Mbps is sufficient for IoT gateways and edge nodes where Gigabit is unnecessary. Compared to integrated MAC-only designs, the LAN8720A adds an analog front-end without inflating BOM cost.
Được đề xuất
Industrial Ethernet Sensor Node
Industrial sensor nodes use the LAN8720A-CP to bridge sensors and actuators to 100BASE-TX networks. Its 0 C to +85 C commercial grade covers indoor enclosures; designers needing outdoor specs select the pin-compatible LAN8720AI-CP-TR. The integrated HP Auto-MDIX eliminates crossover-cable mistakes in field installations, while auto-negotiation ensures robust link-up regardless of partner switch capability. The flexPWR low-power modes reduce idle consumption in duty-cycled deployments.
Được đề xuất
IP Set-Top Box / Home Gateway
Set-top boxes and home gateways leverage the LAN8720A-CP's small 24-QFN footprint to deliver 100 Mbps Ethernet to consumer routers and media players. The variable 1.8/2.5/3.3V I/O allows direct interfacing with most broadband SoCs without external level shifters. Energy-Efficient Ethernet (EEE) support lowers average power consumption during streaming idle periods. The integrated magnetics-friendly line driver simplifies PCB layout around RJ-45 connectors.
Được đề xuất
Networked Printer / Office Equipment
Networked printers and small-office equipment use the LAN8720A-CP as a cost-effective 10/100 Ethernet interface. The 24-QFN package keeps the PCB small, while HP Auto-MDIX simplifies end-user cabling. Auto-negotiation ensures compatibility with legacy 10 Mbps switches that remain in some offices. The commercial temperature grade suits office environments, and flexPWR reduces standby power in Energy Star compliant designs.
Được đề xuất
IP Phone / VoIP Endpoint
IP phones and VoIP endpoints rely on the LAN8720A-CP for reliable 100BASE-TX connectivity with low latency. The RMII interface simplifies MAC integration with DSP-based voice SoCs, while the small QFN package supports ultra-compact handset designs. Auto-negotiation ensures that mixed-vendor switches connect at the highest mutually supported speed. EEE further reduces power during silent intervals in voice calls.
Được đề xuất
Game Console / Consumer Electronics
Game consoles and consumer electronics integrate the LAN8720A-CP to deliver wired network connectivity at minimum BOM cost. The 24-QFN footprint fits compact enclosures, while the commercial 0 to +85 C rating covers indoor operating conditions. flexPWR helps meet strict Energy Star standby targets, and the SMI management interface allows firmware to query link status for diagnostics. Designers benefit from Microchip's mature reference design ecosystem.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LAN8720A-CP — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LAN8720AI-CP-TR | LAN8720A-CP | LAN8742A-CZ |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 24-QFN (4x4 mm) | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-SQFN (compatible footprint, verify land pattern) |
| Data Rate | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps |
| MAC Interface | MII, RMII | MII, RMII | MII, RMII | MII, RMII |
| Operating Temperature | 0 C to +85 C (Commercial) | -40 C to +85 C (Industrial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) |
| Auto-MDIX | HP Auto-MDIX | HP Auto-MDIX | HP Auto-MDIX | HP Auto-MDIX |
| EEE Support | Yes | Yes | Yes | Yes |
Bảo phân biệt quan trọng
- Smallest 24-QFN 10/100 footprint in the LAN family (vsKSZ8081RNACA)
- flexPWR variable I/O voltage (vsLAN8742A)
- Energy-Efficient Ethernet (EEE) built in (vsOlder DP83848-class PHYs)
Ghi chú thiết kế
Place the LAN8720A-CP within 25 mm of the RJ-45 magnetics to keep the differential TX/RX traces short and matched. Use a 50-ohm differential impedance on TXP/TXM and RXP/RXM pairs, and route them over a continuous ground reference with no splits. Stitch the ground plane with vias around the trace edges every 5 mm to control return-path impedance and minimize EMI.
The LAN8720A uses flexPWR with an internal 1.2V LDO from the 3.3V analog supply. Decouple VDDA with a 10uF bulk capacitor and a 0.1uF ceramic placed within 3 mm of the pin. The internal LDO output VDDCR must have its own 0.1uF+10uF decoupling pair at the IC pin. Avoid sharing VDDCR with external loads since internal analog circuits depend on its low-noise regulation.
RMII requires a 50 MHz reference clock at REF_CLK pin with 50 ppm or better stability and jitter under 50 ps RMS. Drive REF_CLK from a clean oscillator - not from a GPIO of the MAC - to ensure IEEE 802.3 timing margins. Keep REF_CLK trace length matched (under 25 mm) and away from switching DC-DC converter nodes to avoid coupling.
Verify the MAC supports RMII before selecting this part - some SoCs expose only MII or RGMII, in which case the LAN8720A-CP must be reconfigured in MII mode with a 25 MHz oscillator feeding the PHY. Do not leave MODE strap pins floating - tie them high or low through 10k resistors per datasheet Table 3 to set PHY address, RMII/MII selection and interrupt polarity deterministically.
Thông tin tuân thủ
RoHS and halogen-free compliance per Microchip datasheet (IEC 61249-2-21). Not AEC-Q100 qualified - not intended for automotive safety-critical use.
