Lattice Semiconductor

LC4064B-5T48C - 64-Macrocell 400 MHz CPLD | Lattice

Name: LC4064B-5T48C - 64-Macrocell 400 MHz CPLD | Lattice
Brand: Lattice Semiconductor
SKU: LC4064B-5T48C

MPN: LC4064B-5T48C ✓ Hoạt động

3.3 V, 2.5 V, and 1.8 V Vdss 48-pin TQFP Package 400 MHz Speed

Yêu cầu báo giá

MOQ: 1 |

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LC4064B-5T48C Tóm tắt

Lattice Semiconductor LC4064B-5T48C is a 64-macrocell in-system-programmable SuperFAST high-density PLD with a maximum operating frequency of 400 MHz, 2.5 ns propagation delay, and a 48-pin TQFP package. The device supports 3.3 V, 2.5 V, and 1.8 V in-system-programmable operation for compact logic, interface, and control designs.

A complex programmable logic device, or CPLD, belongs to the FPGA and CPLD branch of programmable-logic semiconductors. Unlike a mask-programmed fixed logic device, a CPLD retains a user-programmable configuration and combines programmable logic blocks with interconnect resources. The LC4064B family targets designs requiring deterministic timing, rapid field configuration, and moderate logic density without the resource and cost of a large FPGA.

Key features include 64 macrocells, up to four global clock pins, programmable clock-polarity control, and as many as 80 product-term outputs per macrocell. Its 400 MHz maximum operating frequency and 2.5 ns propagation delay provide useful timing margin for address decoding, state-machine control, bus arbitration, data routing, peripheral interfacing, and general-purpose glue logic. In-system programmability allows configuration updates without removing the device from the assembled board.

The LC4064B architecture provides dedicated macrocell logic and programmable routing in a single package. Global clocks can support multiple clock domains, while programmable polarity control helps align rising- or falling-edge logic with external interfaces. Because the verified data identifies the device as a high-density PLD but does not provide detailed I/O counts or timing tables, board-level timing closure must be completed with the manufacturer datasheet and the selected system architecture.

Typical uses include industrial control, peripheral expansion, data-acquisition systems, communications equipment, test-and-measurement instruments, and embedded processor support. The 48-pin TQFP package is also appropriate for prototypes and production boards where a conventional surface-mount footprint is preferred over a fine-pitch BGA. Configuration storage and programming requirements should be evaluated during system design.

For a new layout, verify every pin against the manufacturer datasheet and confirm the configuration device, clock source, and I/O voltage. The available web results explicitly confirm the 48-pin TQFP construction but do not reproduce the complete numbered pin table; accordingly, no unverified pin names are assigned here. Distributor pricing was not published in the supplied results as of 2026-10-28, so commercial availability requires a current quote.

This page consolidates the verified 400 MHz performance, 2.5 ns delay, 64-macrocell density, voltage options, package information, family alternatives, and practical design considerations into an engineer-oriented selection guide. It also distinguishes confirmed manufacturer-family data from parameters that still require verification from the full datasheet.

Bộ thay thế dễ dàng lắp đặt cho LC4064B-5T48C — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.

Các biến thể trong loạt này

Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LC4064B-5T48C (cùng hình factor và footprint) — khác nhau ở Logic Family, Supported Supply Voltages.

LC4064B-5T48I

Lattice Semiconductor

Logic Family: ispMACH 4000B SuperFAST high-density PLD

Supported Supply Voltages: 1.8 V, 2.5 V, and 3.3 V

So sánh với LC4064B-5T48C →

LC4064B-5T48I

✅ Drop-In

Lattice Semiconductor

📦 48-pin TQFP

SuperFAST high-density programmable logic device (CPLD) · ispMACH 4000B · 64 macrocells · 32 I/O · 5 ns · In-system programmable (ISP) · 1.8 V, 2.5 V, and 3.3 V · 48-LQFP (TQFP-48)

Liên hệ để biết giá

Xem tài liệu →

LC4064V-75TN48C

✅ Drop-In

📦 48-pin TQFP

Same 48-pin TQFP footprint and 400 MHz-class LC4064 application class; the V-75 suffix differs from B-5 by two timing-grade steps, with the alternative maximum frequency not stated in the supplied data

📋 Tham chiếu thay thế (không có trong danh mục)

LC4064ZE-7TN48I

✅ Drop-In

📦 48-pin TQFP

Same 48-pin TQFP footprint; the ZE-7 suffix differs from B-5 by two timing-grade steps, while the verified comparison result does not provide the alternative 400 MHz or 2.5 ns ratings

📋 Tham chiếu thay thế (không có trong danh mục)

LC4064B-4T48C

✅ Drop-In ⚠️ Thông số chưa được xác minh

📦 48-pin TQFP

Same LC4064B architecture and 48-pin TQFP footprint; the -4 speed suffix is one timing-grade step slower than the target -5 grade, while numeric alternative timing is not stated in the supplied data

📋 Tham chiếu thay thế (không có trong danh mục)

LC4064B-6T48C

✅ Drop-In ⚠️ Thông số chưa được xác minh

📦 48-pin TQFP

Same LC4064B architecture and 48-pin TQFP footprint; the -6 speed suffix is one timing-grade step faster than the target -5 grade, while numeric alternative timing is not stated in the supplied data

📋 Tham chiếu thay thế (không có trong danh mục)

LC4064B-5T48C Tỷ lệ tối đa & tính chất điện

Device Type	In-System Programmable SuperFAST High-Density PLD
Macrocell Count	64 macrocells
Maximum Operating Frequency	400 MHz
Propagation Delay	2.5 ns
Supported Supply Voltages	3.3 V, 2.5 V, and 1.8 V
Configuration Method	In-system programmable
Global Clock Pins	Up to 4 pins
Clock Polarity Control	Programmable
Product-Term Outputs per Macrocell	Up to 80 PTs per output
Package Type	48-pin TQFP
Số chân	48 pins
Kiểu lắp đặt	Surface mount
Logic Family	SuperFAST high-density PLD family
Programmable Logic Type	Complex programmable logic device (CPLD)

Hướng dẫn cấu hình chân LC4064B-5T48C 48-pin tqfp

Cấu hình chân cho LC4064B-5T48C (48-pin tqfp gói). IC số này bao gồm chân GPIO, giao diện truyền thông (UART, SPI, I2C) và chân nguồn. Tham khảo tài liệu thông số kỹ thuật của nhà sản xuất để biết các chức năng chân thay thế và tùy chọn cấu hình. Cực kỳ quan trọng cho thiết kế hệ thống tích hợp và lập trình PCB.

Bảng cấu hình chân 48-pin tqfp cho LC4064B-5T48C

Không có dữ liệu chân cụ thể sẵn có cho LC4064B-5T48C.

Tham khảo: tài liệu kỹ thuật cho cấu hình chân đầy đủ.

Ứng dụng tiêu biểu

LC4064B-5T48C phù hợp cho 6 Áp dụngs: Industrial Control Logic, Processor Peripheral Interface, Data Acquisition Interface, Communications Equipment Control, Test and Measurement Control, Embedded System Glue Logic.

🏭

Industrial Control Logic

The LC4064B-5T48C fits industrial control blocks that require deterministic combinational and sequential logic without a large FPGA. Its 64 macrocells support compact state machines, interlocks, command decoding, and discrete control functions, while the 400 MHz maximum operating frequency and 2.5 ns propagation delay provide timing margin for common control paths. The four global clock inputs can organize related sequential sections with programmable polarity. Because the verified data does not provide the complete I/O count or temperature range, the implementation must be checked against the exact 48-pin TQFP datasheet before assigning industrial field I/O.

Được đề xuất

🖥️

Processor Peripheral Interface

The LC4064B-5T48C is useful when a processor needs additional address decode, chip-select generation, interrupt routing, or protocol-state logic. Its 64 macrocells can consolidate multiple fixed-interface functions, and the 400 MHz maximum operating frequency is substantially above many low-speed peripheral buses. The 2.5 ns propagation-delay specification also supports tightly timed control paths around a host processor. Use one global clock where the host interface is synchronous, reserve other globals only after checking timing, and validate that the selected voltage and I/O standards match the processor and attached peripherals.

Được đề xuất

STM32F429VIT6TR · STMicroelectronics ATMEGA1284P-AUR · Microchip Technology

🔧

Data Acquisition Interface

The LC4064B-5T48C can implement deterministic acquisition-control logic, channel multiplexing sequences, trigger qualification, and data-routing functions in instrumentation systems. Its 64 macrocells are appropriate for moderate fan-out and control density, while the 400 MHz maximum operating frequency allows acquisition state machines to operate well above typical slow sensor-interface rates. The 48-pin TQFP package simplifies prototyping and conventional surface-mount assembly. Exact input thresholds, output-drive capability, and available user I/O must be verified from the datasheet because those values are not present in the supplied web snippets.

Được đề xuất

TLV1504ID · Texas Instruments TMS320C10FNLR · Texas Instruments

🌐

Communications Equipment Control

The LC4064B-5T48C is suitable for communications equipment that needs deterministic framing, command parsing, channel selection, or interface timing around higher-level processors. Its 64 macrocells support compact protocol state machines and routing logic, while up to four global clocks can support related receive, transmit, and service domains with programmable polarity. The 2.5 ns propagation delay provides useful margin for short combinational paths and registered transfers. Before implementation, confirm the device's I/O standard and timing against the actual communications transceiver, and avoid assuming that another LC4064 suffix has identical voltage or timing behavior.

Được đề xuất

TCAN334DR · Texas Instruments SI8244CB-D-IS1R · Skyworks Solutions

🔧

Test and Measurement Control

The LC4064B-5T48C can implement sequencers, instrument-control decoding, trigger paths, and front-panel logic where predictable timing is more important than very high programmable-logic density. The 64 macrocells allow several compact control channels to coexist, and the 400 MHz maximum operating frequency supports high-speed state transitions. Programmable clock polarity allows clocking to be aligned with the polarity used by counters, latches, or external test logic. The verified data does not state the operating-temperature grade or complete pinout, so both environmental suitability and unused-pin behavior require direct datasheet confirmation.

Được đề xuất

TMS320C10FNLR · Texas Instruments MAX232DR · Texas Instruments

🧩

Embedded System Glue Logic

The LC4064B-5T48C is appropriate for glue logic that expands a microcontroller or DSP footprint with address decoding, multiplexing, latch controls, arbitration, and boot sequencing. Its 64 macrocells provide more room than a handful of discrete gates, while in-system programmability allows corrections without board respinning. The 48-pin TQFP footprint supports conventional PCB assembly and inspection. At 400 MHz maximum operating frequency and 2.5 ns propagation delay, the device can handle high-speed control paths, but designers should preserve configuration access and validate every I/O voltage against the connected embedded subsystem.

Được đề xuất

STM32F429ZGT6TR · STMicroelectronics ATMEGA128-16AUR · Microchip Technology

Tóm tắt các sản phẩm được đề xuất

What are the key specifications of LC4064B-5T48C that engineers should know?

The LC4064B-5T48C is a 64-macrocell CPLD with a 400 MHz maximum operating frequency, 2.5 ns propagation delay, and a 48-pin TQFP package. According to the Lattice Semiconductor datasheet results, it supports 3.3 V, 2.5 V, and 1.8 V in-system-programmable operation. It also provides up to four global clock pins, programmable clock polarity, and as many as 80 product-term outputs per macrocell. These characteristics make it relevant to deterministic control logic, bus arbitration, state-machine, and peripheral-interface designs that require field-reconfigurable logic without moving to a larger FPGA.

Where can I download the LC4064B-5T48C datasheet PDF?

The LC4064B-5T48C datasheet can be accessed through the Lattice Semiconductor document linked at https://www.alldatasheet.com/datasheet-pdf/pdf/169217/LATTICE/LC4064B-5T48C.html. Additional indexed copies include Datasheet4U and DatasheetQ, with the DatasheetQ result identifying a 17-page document. The indexed source identifies the device as a 3.3 V, 2.5 V, and 1.8 V in-system-programmable SuperFAST high-density PLD. Before releasing a design, verify pin assignments, electrical limits, timing tables, and configuration requirements against the complete manufacturer document.

Where can I find the LC4064B-5T48C pinout?

The LC4064B-5T48C pinout is contained in the 48-pin TQFP datasheet and the package drawing available through the linked manufacturer-document index. The verified results confirm that this orderable configuration uses a 48-pin TQFP package and that a separate pinout view is available, but they do not reproduce the complete numbered pin table. For that reason, this listing does not invent individual pin names. Download the datasheet and cross-check every power pin, configuration pin, clock input, and user I/O against the exact package drawing before laying out or modifying a PCB.

What is the LC4064B-5T48C operating frequency and propagation delay?

The LC4064B-5T48C supports a maximum operating frequency of 400 MHz and has a stated propagation-delay value of 2.5 ns. According to the indexed Lattice Semiconductor datasheet, these are the headline timing specifications for the -5 speed grade and its SuperFAST high-density PLD architecture. Actual system timing can differ because interconnect delay, pin loading, logic levels, clock distribution, and the selected product-term path contribute to the final path delay. Use the manufacturer timing model and worst-case operating conditions for final timing closure.

How many macrocells and global clocks does the LC4064B-5T48C have?

The LC4064B-5T48C contains 64 macrocells and provides up to four global clock pins with programmable clock-polarity control. The verified Lattice family description also states that the architecture can provide as many as 80 product terms per output. These resources are intended for compact combinational logic, registered control functions, bus decoding, address qualification, and peripheral state machines. The four global clocks are particularly useful when a design requires one or more distributed clock domains, but each domain must still be constrained and checked for correct polarity and timing.

What can replace the LC4064B-5T48C on the same PCB?

A genuine replacement must retain the 48-pin TQFP footprint, pin assignment, supported supply voltages, and compatible timing. The verified cross-reference results identify LC4064V-75TN48C, LC4064ZE-7TN48I, and LC4064B-5T48I as candidates for engineering comparison, while same-family -4 and -6 timing grades are possible alternatives within the LC4064B family. None should be populated without checking the complete pin tables and AC timing tables. The available data does not prove that every candidate is a complete drop-in equivalent, so board changes and programming-file compatibility must be confirmed first.

Is LC4064B-5T48C the same as LC4064V-75TN48C?

No conclusion of equivalence should be made solely from the shared LC4064 family name and 48-pin TQFP package. The LC4064V-75TN48C uses a different series and speed designation, while the LC4064B-5T48C is a SuperFAST high-density PLD rated at 400 MHz with 2.5 ns propagation delay. The cross-reference search identifies the LC4064V part for comparison but does not provide a verified complete pin-for-pin or timing-equivalence statement. Compare power pins, configuration pins, I/O standards, input thresholds, output behavior, and timing before treating it as a drop-in replacement.

What is the best Lattice Semiconductor equivalent for LC4064B-5T48C?

The closest verified same-brand candidates are LC4064B-5T48I, LC4064V-75TN48C, and LC4064ZE-7TN48I because the supplied cross-reference results explicitly connect them to the LC4064B-5T48C family or direct comparison. The LC4064B-5T48I is the most natural starting point because it retains the B-5 timing designation and 48-pin TQFP construction, with a different package temperature suffix. The LC4064V and LC4064ZE devices may differ in voltage options, density, architecture, and timing. Verify the full datasheets before selecting any equivalent.

Where can I buy LC4064B-5T48C online?

The LC4064B-5T48C is listed for procurement through Mouser, Octopart, and multiple component distributors, including Xecor, Nantian Electronics, and Veswin Electronics. The verified results provide live product links but do not expose exact unit prices or confirmed warehouse quantities. As of 2026-10-28, pricing should therefore be requested from a distributor rather than inferred from the search snippets. When requesting a quote, include the 48-pin TQFP package, target quantity, and required delivery date so the distributor can confirm whether the exact -5 speed grade and temperature suffix are available.

What is the price of LC4064B-5T48C?

No exact LC4064B-5T48C unit price is published in the supplied distributor results as of 2026-10-28, so a defensible numeric quote cannot be stated. Mouser identifies the part as an Lattice CPLD, and Octopart offers a price-comparison page, but the snippets do not include the actual price tiers. Request a current quotation from Mouser or another authorized distributor using the full MPN LC4064B-5T48C. Confirm quantity breaks, tax, shipping, and stock at the same time, because distributor pricing and availability can change without notice.

What is the lead time for LC4064B-5T48C?

The verified web data does not provide a firm LC4064B-5T48C lead time as of 2026-10-28. Mouser and several distributor listings indicate that the part is cataloged, but catalog presence alone does not prove that inventory is immediately available. Ask the selected distributor for stock, scheduled delivery, and any minimum-order quantity. If production continuity is critical, specify the exact MPN rather than a generic LC4064 family designation, because timing grade, package suffix, and operating-temperature classification can produce different inventory positions.

Is LC4064B-5T48C in stock?

The available search results do not explicitly state that LC4064B-5T48C is in stock, even though Mouser and several distributors list the component. XAIPART therefore treats availability as unknown rather than claiming in-stock status. Check the Mouser product page or Octopart aggregation for live quantity, or submit a request for quotation with your required quantity and date. The part is identified as a 48-pin TQFP, 400 MHz, 64-macrocell CPLD, but accurate sourcing must still be confirmed at the distributor transaction level.

When should I choose LC4064B-5T48C over a slower LC4064B timing grade?

Choose the LC4064B-5T48C when a design benefits from the stated 400 MHz maximum operating frequency and 2.5 ns propagation delay rather than only functional equivalence. Its four global clocks and programmable polarity also suit multi-clock control logic. A slower family timing grade may be appropriate when the design does not require the -5 grade's timing margin, but lower propagation-delay margin can affect system frequency, external-interface timing, and the number of pipeline stages required. Choose based on the full path-timing report rather than a nominal product-family label alone.

Is LC4064B-5T48C suitable for industrial control and peripheral interfacing?

Yes, the LC4064B-5T48C is technically suitable for many industrial-control, bus-control, state-machine, and peripheral-interfacing tasks that fit within 64 macrocells. Its 400 MHz maximum operating frequency, 2.5 ns propagation delay, programmable global clocks, and 3.3 V, 2.5 V, or 1.8 V operation support compact deterministic logic implementations. Suitability still depends on the operating-temperature grade, available I/O count, logic depth, and timing closure; the verified results do not provide those complete electrical limits or the operating-temperature range.

What design considerations apply to an LC4064B-5T48C implementation?

The principal considerations are configuration support, clocking, I/O standards, and timing margin. Use the 3.3 V, 2.5 V, or 1.8 V capability appropriate to the connected logic, preserve the required configuration path, and constrain every global clock and polarity assignment. The device can operate at 400 MHz with 2.5 ns propagation delay, but final timing depends on the selected logic path. Review power sequencing, decoupling, unused pins, configuration behavior, and the package pin table directly in the manufacturer datasheet before schematic sign-off.

What compliance and qualification information is available for LC4064B-5T48C?

RoHS, REACH, AEC-Q100, lead-free, halogen-free, and conflict-minerals status cannot be confirmed from the supplied verified snippets for LC4064B-5T48C. The comparison result for LC4064ZE-7TN48I mentions RoHS and REACH comparison fields, but it does not establish the status of this exact orderable MPN. Treat every compliance field as unknown until the manufacturer product page, declaration, or lot documentation is checked. Automotive qualification should not be inferred merely from the industrial -5T48I-style family naming or from another LC4064 variant.

Dữ liệu tham khảo kỹ thuật cho LC4064B-5T48C — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.

Hướng dẫn chọn lựa

Choose the LC4064B-5T48C when the design fits within 64 macrocells and benefits from the verified 400 MHz maximum operating frequency, 2.5 ns propagation delay, four global clocks, and 3.3 V, 2.5 V, or 1.8 V in-system-programmable operation. It is particularly suitable for deterministic state machines, address decoding, peripheral control, and processor glue logic. Select LC4064B-5T48I when the system needs the same -5 timing class but a different verified temperature-class suffix. Consider LC4064B-4T48C when lower timing performance is acceptable, and LC4064B-6T48C when additional speed margin is desirable, provided the full pin and timing tables confirm compatibility. LC4064V-75TN48C and LC4064ZE-7TN48I are same-package candidates but differ in family or speed designation; use them only after checking voltage support, macrocell capacity, configuration architecture, and timing. For every alternative, preserve the 48-pin TQFP footprint and verify that the configuration file, pin assignment, and system timing remain valid.

So sánh với các sản phẩm thay thế

Tham số	Sản phẩm này	LC4064B-5T48I	LC4064V-75TN48C	LC4064ZE-7TN48I	LC4064B-4T48C	LC4064B-6T48C
Package	48-pin TQFP	48-pin TQFP - same	48-pin TQFP - same	48-pin TQFP - same	48-pin TQFP - same	48-pin TQFP - same
Brand	Lattice Semiconductor	Lattice Semiconductor	Lattice Semiconductor	Lattice Semiconductor	Lattice Semiconductor	Lattice Semiconductor
Device Series	LC4064B	LC4064B	LC4064V	LC4064ZE	LC4064B	LC4064B
Speed Designation	-5	-5	-75	-7	-4	-6

Bảo phân biệt quan trọng

Highest-speed timing grade among the specifically compared LC4064B candidates (vsLC4064B-4T48C)
Same speed designation with a different package temperature suffix (vsLC4064B-5T48I)
Directly verified 64-macrocell resource density (vsLC4064ZE-7TN48I)
Multi-voltage in-system-programmable family support (vsLC4064V-75TN48C)

Ghi chú thiết kế

Do not treat every LC4064 suffix as electrically identical. The target uses a -5 speed designation and a C package suffix, while alternatives include different series, speed grades, and temperature designations. Before substituting a device, compare the complete numbered pin table, core supply requirements, I/O voltage options, configuration pins, and AC timing tables. The supplied web results establish the shared 48-pin TQFP construction for the listed candidates, but they do not prove identical configuration behavior or timing.

Determine the actual core and I/O supply arrangement from the full manufacturer datasheet before connecting the 48-pin TQFP. The family supports 3.3 V, 2.5 V, and 1.8 V operation, but those figures do not by themselves identify which supply pins may be tied together or which voltage applies to every I/O bank. Use the exact recommended decoupling network, power-up ordering, and configuration requirements shown in the datasheet and reference design. In-system programmability should not be interpreted as permission to violate supply sequencing.

Route all four available global-clock inputs with controlled impedance, short stubs, and solid return paths. Although the device is rated up to 400 MHz, the 2.5 ns propagation-delay figure does not guarantee that every external clock edge is clean at 400 MHz. Confirm clock polarity in the design, avoid unnecessary fanout, separate sensitive or asynchronous inputs from high-current outputs, and run timing analysis with the actual board parasitics and external load assumptions. If clock quality is uncertain, lower the interface rate rather than relying only on nominal CPLD timing.

Place configuration-support components and decoupling capacitors close to their associated pins, and follow the manufacturer's TQFP land pattern and pin-1 orientation exactly. Keep the 48-pin footprint mechanically compatible with the listed candidates, but do not assume that physical compatibility guarantees logic compatibility. Review unused-pin treatment, configuration behavior during reset, and programming-interface access in the pin table. A footprint comparison should supplement, not replace, a complete electrical and timing review of any alternative.

Thông tin tuân thủ

RoHS

Unknown

REACH

Unknown

AEC-Q100

Unknown

Không chì

Unknown

Không halogen

Unknown

Khoáng vật xung đột

Unknown

The supplied verified snippets do not explicitly establish RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status for the exact LC4064B-5T48C orderable MPN. Compliance claims for other LC4064 variants must not be transferred automatically to this part.

Dữ liệu được xác minh vào: 2026-10-28 — dữ liệu được xác minh và quản lý bởi đội ngũ kỹ thuật phần cứng của XAIPART

Nguồn: Distributor, Distributor, Distributor, Distributor, Octopart, Distributor, Distributor, Distributor, Distributor, Distributor

Tìm kiếm liên quan

LC4064B-5T48C LC4064B-5T48C datasheet PDF Lattice LC4064B-5T48C CPLD LC4064B-5T48C 400 MHz 2.5 ns LC4064B-5T48C 48-pin TQFP LC4064B-5T48C pinout LC4064B-5T48C price LC4064B-5T48C buy online LC4064B-5T48C lead time and stock LC4064B-5T48C drop-in replacement LC4064B-5T48C vs LC4064V-75TN48C LC4064B-5T48C vs LC4064ZE-7TN48I 64 macrocell in-system programmable CPLD 400 MHz CPLD industrial control CPLD for processor peripheral interface

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Lattice Semiconductor LC4064B-5T48C LC4064B-5T48I LC4064V-75TN48C LC4064ZE-7TN48I LC4064B-4T48C LC4064B-6T48C CPLD complex programmable logic device FPGA and CPLD programmable logic semiconductor SuperFAST high-density PLD in-system programmable macrocell product term global clock clock polarity control propagation delay maximum operating frequency 3.3 V 2.5 V 1.8 V TQFP-48 surface mount address decoding state machine peripheral interface

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