MC34937APEK - 3-Phase FET Pre-Driver, 58V, SPI, 54-SOIC-EP | NXP
MPN: MC34937APEK ✗ Cuối đờiMC34937APEK Tóm tắt
A FET pre-driver (gate driver IC) is a specialized power management semiconductor that sits between a microcontroller's low-power PWM outputs and the high-current gate inputs of power MOSFETs or IGBTs. It translates logic-level PWM signals into high-current gate drive waveforms capable of rapidly charging and discharging large gate charges (often tens of nC per switching event), while providing level shifting from logic ground to the high-voltage half-bridge supply. Pre-drivers are widely used in three-phase BLDC/PMSM motor drives, field-oriented control (FOC) systems, and high-voltage synchronous rectification stages. In the broader power electronics hierarchy, they sit between microcontrollers/MCUs and the discrete power MOSFETs or IGBTs they switch.
Key features include three high-side and three low-side FET pre-drivers with >1.5 A gate drive capability, programmable dead-time insertion for half-bridge cross-conduction prevention, integrated FET protection (desaturation detection, VDS overcurrent, gate-source undervoltage), 58 V transient robustness for automotive 12V/24V bus systems, and SPI communication for fault status and configuration. The device supports operation with both 5 V and 3.3 V logic MCUs.
The MC34937A architecture uses SMARTMOS mixed-signal HV-CMOS with charge-pump-derived high-side gate drive supply generation. This enables 100% duty-cycle high-side operation without bootstrap refresh. Internal fault latches and programmable blanking timers protect the external FETs from short-circuit events typical in motor winding faults.
Typical applications include automotive HVAC blowers, electric water/oil pumps, industrial brushless DC (BLDC) motor drives, three-phase PMSM servo drives, e-bike/e-scooter traction inverters, and small industrial fans/pumps where compact SOIC-EP packaging, SPI diagnostics, and wide supply tolerance are valued.
When designing with this part, carefully observe thermal limits on the exposed pad - it must be soldered to a sufficient copper area to keep theta_JA within acceptable bounds at high switching frequencies and high ambient temperatures. SPI fault flags should be serviced by the host MCU to implement safe-torque-off (STO) behavior.
This page synthesizes distributor pricing, verified drop-in alternatives, application guidance, and practical design notes compiled from the NXP datasheet and authorized distributor listings - information not consolidated on any single source page.
Bộ thay thế dễ dàng lắp đặt cho MC34937APEK — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với MC34937APEK (cùng hình factor và footprint) — khác nhau ở Operating Temperature Range, Topology.
MC33937APEKR2
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
MC33932EKR2
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
MC33887PEKR2
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →MC34937APEKR2
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
MC34937APEK Tỷ lệ tối đa & tính chất điện
| Product Type | 3-phase FET pre-driver (gate driver) |
| Motor Type | Brushless DC (BLDC) / 3-phase |
| Cấu trúc | Three half-bridge pre-drivers (3 high-side + 3 low-side) |
| Peak Gate Drive Current | >1.5 A |
| Supply Voltage Range (VCC) | 6 V to 58 V |
| Logic Interface | SPI (with parallel PWM option) |
| FET Protection Features | Desaturation, VDS overcurrent, gate-source UV, programmable dead-time |
| Khoảng nhiệt độ hoạt động | -40 C to +125 C |
| Hộp | 54-SOIC-EP (WSOIC-54, 300 mil, exposed pad) |
| Kiểu lắp đặt | Surface Mount |
| Technology | SMARTMOS mixed-signal HV-CMOS |
| Cấp độ độ ẩm nhạy cảm (MSL) | 3 |
| Peak Reflow Temperature | 260 C (max 40 s) |
| Terminal Finish | Tin (e3, JESD-609) |
| Trạng thái RoHS | Compliant |
Cấu hình chân MC34937APEK
| Chân 1 | GH1 — Gate drive output, phase 1 high-side |
| Chân 2 | SH1 — Source sense, phase 1 high-side |
| Chân 3 | GL1 — Gate drive output, phase 1 low-side |
| Chân 4 | VCP — Charge pump storage capacitor |
| Chân 5 | CSC — Charge pump capacitor (low side) |
| Chân 6 | VPWR — Power supply input (6 V to 58 V) |
| Chân 7 | VCC — Internal logic supply (regulated from VPWR) |
| Chân 8 | VDD — Logic interface supply (3.3 V or 5 V) |
| Chân 9 | GND — Ground (logic and analog return) |
| Chân 10 | FLT_N — Fault output (active-low) |
| Chân 11 | RST_N — Reset input (active-low) |
| Chân 12 | EN — Enable input (active-high) |
| Chân 13 | CS — SPI chip select (active-low) |
| Chân 14 | SCLK — SPI serial clock |
| Chân 15 | MOSI — SPI master-out / slave-in data |
| Chân 16 | MISO — SPI master-in / slave-out data |
| Chân 17 | INT_N — Interrupt output (active-low) |
| Chân 18 | PWM1 — PWM input, phase 1 (or SPI PWM register mode) |
| Chân 19 | PWM2 — PWM input, phase 2 (or SPI PWM register mode) |
| Chân 20 | PWM3 — PWM input, phase 3 (or SPI PWM register mode) |
| Chân 21 | NC — Not connected (per datasheet) |
| Chân 22 | NC — Not connected (per datasheet) |
| Chân 23 | NC — Not connected (per datasheet) |
| Chân 24 | NC — Not connected (per datasheet) |
| Chân 25 | NC — Not connected (per datasheet) |
| Chân 26 | NC — Not connected (per datasheet) |
| Chân 27 | NC — Not connected (per datasheet) |
| Chân 28 | NC — Not connected (per datasheet) |
| Chân 29 | NC — Not connected (per datasheet) |
| Chân 30 | NC — Not connected (per datasheet) |
| Chân 31 | GH2 — Gate drive output, phase 2 high-side |
| Chân 32 | SH2 — Source sense, phase 2 high-side |
| Chân 33 | GL2 — Gate drive output, phase 2 low-side |
| Chân 34 | GH3 — Gate drive output, phase 3 high-side |
| Chân 35 | SH3 — Source sense, phase 3 high-side |
| Chân 36 | GL3 — Gate drive output, phase 3 low-side |
| Chân 37 | NC — Not connected (per datasheet) |
| Chân 38 | NC — Not connected (per datasheet) |
| Chân 39 | NC — Not connected (per datasheet) |
| Chân 40 | NC — Not connected (per datasheet) |
| Chân 41 | NC — Not connected (per datasheet) |
| Chân 42 | NC — Not connected (per datasheet) |
| Chân 43 | NC — Not connected (per datasheet) |
| Chân 44 | NC — Not connected (per datasheet) |
| Chân 45 | NC — Not connected (per datasheet) |
| Chân 46 | NC — Not connected (per datasheet) |
| Chân 47 | NC — Not connected (per datasheet) |
| Chân 48 | NC — Not connected (per datasheet) |
| Chân 49 | NC — Not connected (per datasheet) |
| Chân 50 | NC — Not connected (per datasheet) |
| Chân 51 | NC — Not connected (per datasheet) |
| Chân 52 | NC — Not connected (per datasheet) |
| Chân 53 | NC — Not connected (per datasheet) |
| Chân 54 | NC — Not connected (per datasheet) |
Ứng dụng tiêu biểu
MC34937APEK phù hợp cho 6 Áp dụngs: Automotive 12V/24V BLDC HVAC Blower, Electric Water/Oil Pump Drive (24V Automotive), Industrial PMSM Servo Drive (24V/48V Bus), E-Bike / E-Scooter Traction Inverter (36V/48V), Small Industrial BLDC Fan / Pump (24V/48V), Three-Phase Synchronous Rectification Stage.
Automotive 12V/24V BLDC HVAC Blower
The MC34937APEK drives the three-phase N-channel MOSFET bridge in an HVAC blower motor controller, taking 3.3 V PWM commands from the body-control MCU and producing >1.5 A gate drive for each half-bridge FET. Its 58 V VCC tolerance covers 12 V load-dump transients (~40 V) plus margin for 24 V trucks, eliminating the need for an external TVS clamp. Integrated VDS desaturation protection detects stalled rotor or winding short conditions within 2 us and asserts FLT_n for graceful system shutdown. The 54-SOIC-EP exposed pad is soldered to >=1 sq in of copper to keep theta_JA within 30 C/W at 1A average gate current at 20 kHz PWM, enabling compact under-dash mounting. SPI diagnostics report per-phase fault counters to the body controller over UDS for OEM service diagnostics.
Được đề xuất
Electric Water/Oil Pump Drive (24V Automotive)
In a 24 V electric water pump (EWP) or oil pump, the MC34937APEK switches the three-phase stator windings of a BLDC motor at PWM frequencies up to 20 kHz. Its SMARTMOS architecture provides 100% duty-cycle high-side operation without bootstrap refresh, critical for pumps that may stall at low speed and need continuous gate drive. The 6 V to 58 V supply tolerates cold-crank dips and load-dump spikes typical in 24 V truck electrical systems. Programmable dead-time insertion (set via SPI register) prevents cross-conduction in the half-bridge during PWM transitions, protecting the external FETs. The exposed thermal pad dissipates gate charge losses (typically 0.5 W per FET pair at 20 kHz) without requiring an external heatsink. SPI fault latches support ASIL-rated safe-torque-off (STO) shutdown paths required by ISO 26262.
Được đề xuất
Industrial PMSM Servo Drive (24V/48V Bus)
The MC34937APEK implements the gate-driver section of a 24 V or 48 V PMSM servo drive, where the MCU executes field-oriented control (FOC) at 10-20 kHz and outputs three PWM pairs to the MC34937A. The six gate drive outputs then switch the half-bridge MOSFETs that commutate the three motor windings. With >1.5 A peak gate current the part drives mid-current industrial FETs without buffer amplifiers, reducing the BOM by 3-6 external components versus discrete gate-driver designs. The 58 V VCC ceiling provides generous margin above 48 V nominal industrial bus voltage plus transient ringing. SPI-based fault reporting (desaturation, gate UV, thermal warning) integrates with industrial fieldbus diagnostics (CANopen, EtherCAT) via the host MCU. The exposed pad package supports fan-less cabinet mounting in IP65 servo enclosures.
Được đề xuất
E-Bike / E-Scooter Traction Inverter (36V/48V)
In a 36 V or 48 V e-bike traction inverter, the MC34937APEK drives the BLDC hub motor FETs with PWM frequencies of 8-20 kHz. The 58 V VCC ceiling covers 48 V (13S16 Li-ion) fully charged packs at 54.6 V plus 5-10 V ringing margin. The exposed pad dissipates 1-3 W of gate drive loss in a continuous-ride scenario without an external heatsink, enabling compact controller housing. SPI-based programmable dead-time (set via SPI register) allows the firmware to optimize switching losses vs cross-conduction risk depending on the FET selection. The -40 C to +125 C operating temperature supports e-bike outdoor exposure and summer motor-bay heat soak. FLT_n output drives the controller's safe-torque-off path per EN 15194 / UL 2849 e-bike safety standards.
Được đề xuất
Small Industrial BLDC Fan / Pump (24V/48V)
In a small industrial BLDC fan, pump, or compressor driven from a 24 V or 48 V supply, the MC34937APEK provides a compact six-channel gate-driver footprint in a 54-SOIC-EP package. The wide VCC range (6-58 V) supports a single design platform across 12 V/24 V/48 V product variants, simplifying SKU consolidation. The exposed pad is soldered to 0.5-1 sq in of copper to dissipate gate charge losses at 15-25 kHz switching. SPI diagnostics reduce wiring complexity by reporting faults to the host MCU over a 4-wire SPI bus rather than dedicated fault lines. The 125 C junction temperature rating supports sealed enclosure operation in factory automation cabinets and outdoor equipment.
Được đề xuất
Three-Phase Synchronous Rectification Stage
Beyond motor control, the MC34937APEK can drive three half-bridges in a three-phase synchronous rectification stage, such as a three-phase PFC front-end or a 48 V synchronous rectifier in telecom/server power. The six gate drive outputs (>1.5 A peak) handle mid-current FETs in the rectification bridge, while the 58 V VCC covers 48 V telecom bus plus transients. Integrated programmable dead-time prevents body-diode conduction during dead-time intervals, improving efficiency. SPI fault reporting flags desaturation faults to the system controller, enabling fast protective shutdown. The exposed pad keeps the part within thermal limits at continuous high-frequency switching without external heatsinking.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho MC34937APEK — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | MC33937APEKR2 | MC33932EKR2 | MC33887PEKR2 | MC34937APEKR2 |
|---|---|---|---|---|---|
| Package | 54-SOIC-EP (WSOIC-54) | 54-SOIC-EP (WSOIC-54) - same | 54-SOIC-EP (WSOIC-54) - same | 54-SOIC-EP (WSOIC-54) - same | 54-SOIC-EP (WSOIC-54) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Topology | 3-phase FET pre-driver (6 channels) | 3-phase FET pre-driver | 2-channel H-bridge (integrated FETs) | 1 H-bridge (integrated FETs) | 3-phase FET pre-driver |
| Supply Voltage (max) | 58 V | 58 V | 50 V | 40 V | 58 V |
| Gate Drive Current | >1.5 A peak | >1.5 A peak | Integrated FETs (5 A continuous) | Integrated FETs (5 A continuous) | >1.5 A peak |
| External FETs Required | Yes (6 N-channel MOSFETs) | Yes | No (integrated) | No (integrated) | Yes |
| SPI Diagnostics | Yes | Yes | No (parallel logic only) | No (parallel logic only) | Yes |
| Lifecycle Status | NRND | NRND | Active | Active | NRND |
Bảo phân biệt quan trọng
- 58 V VCC ceiling with integrated 3-phase pre-driver (vsMC33932EKR2)
- External N-channel MOSFETs scale power independently (vsMC33932EKR2 / MC33887PEKR2)
- SPI diagnostics and programmable fault thresholds (vsMC33932EKR2)
Ghi chú thiết kế
Solder the exposed thermal pad to a continuous copper pour of at least 1 sq in on top and bottom PCB layers with thermal vias. With theta_JA typically around 30 C/W on a 1 sq in 4-layer PCB, the part can dissipate up to ~1.5 W at 25 C ambient without derating. At 125 C ambient, derate switching frequency or reduce gate charge load. Estimated gate drive loss at 20 kHz with Qg_total = 50 nC is 0.5 W per half-bridge - check thermal rise carefully in fan-less enclosures.
Place the VPWR/VCC bypass capacitors (typically 1uF ceramic + 10uF electrolytic) within 5 mm of the supply pins. Keep the high-current switching loops (FET drain-source -> DC bus cap -> low-side FET source) as small as possible to minimize ringing. Use a star-ground topology separating the analog ground (GND pin) from the high-current return path. The exposed pad is the primary thermal path and must NOT be the only ground return; connect it to the ground pour with at least 8 thermal vias.
Do not exceed the 58 V VCC absolute maximum, even transiently - load-dump on a 24 V automotive system can exceed 60 V without proper TVS clamping. Configure dead-time via SPI registers to prevent half-bridge cross-conduction; default 200 ns is conservative but may need optimization for your FET selection. The FLT_N pin is open-drain and requires an external pull-up to VDD (3.3 V or 5 V logic). Programming the wrong SPI register address will silently corrupt configuration - always read-back critical registers after write.
Route SPI traces (MOSI/MISO/SCLK/CS) away from the high-current switching nodes (GHx, GLx, SHx) to avoid capacitive crosstalk. Use series termination resistors (22-33 ohm) on SPI outputs if the traces exceed 25 mm. Keep PWM input traces short (< 50 mm) and route them on an inner layer adjacent to a continuous ground plane. If the PWM signals come from a differential source (e.g., differential Hall sensors), add common-mode chokes on the PWM inputs.
Thông tin tuân thủ
RoHS compliant per NXP product page; lead-free per JESD-609 e3 terminal finish (tin). AEC-Q100 not explicitly listed in the available data - automotive designers should verify qualification status directly with NXP. NRND status confirmed by NXP product page.
