MX574ALEWI+CDR - 12-Bit SAR ADC, 25us, 28-SOIC | Maxim
MPN: MX574ALEWI+CDR ✓ Hoạt độngMX574ALEWI+CDR Tóm tắt
An SAR ADC is a type of data converter that uses a binary search algorithm and an internal capacitive DAC to digitize an analog input. Each conversion takes a fixed number of clock cycles, and the architecture delivers excellent linearity and no pipeline delay, which makes it well-suited to multiplexed data-acquisition front-ends, industrial instrumentation, and process control loops where predictable latency matters more than raw sample rate.
Key features include 12-bit resolution, +/-1 LSB maximum linearity error, an internal buried-Zener reference trimmed for low drift, and a tri-state output buffer for direct connection to 8-bit or 16-bit microprocessor buses. The device accepts 0 to +10 V or 0 to +20 V unipolar analog input ranges (and +/-5 V or +/-10 V bipolar ranges when configured), and the parallel byte/word output interface simplifies integration with 8051, 68HC11, and DSP processors.
The MX574A uses a precision laser-trimmed thin-film resistor ladder and an on-chip temperature-compensated bandgap reference; successive-approximation registers perform a binary search to produce the digital output. Internal timing is generated by an on-chip oscillator, removing the need for an external conversion clock, while the reference buffer can drive external loads up to 1.5 mA.
Typical applications include process control front-ends, multi-channel data-acquisition boards, instrumentation and test equipment, digital panel meters, and any 8051/68HC11/DSP-based system that needs a complete, no-external-component ADC. The 25us conversion time places the part in the medium-speed SAR category - faster than integrating ADCs but slower than 1 MHz successive-approximation converters such as the AD574A.
Design tip: keep the analog input bandwidth well below the device's aperture limit and place a small RC filter (typically 100 ohm + 1 nF) ahead of the analog input pin to suppress charge-injection transients from the internal DAC switching. Decouple VCC and VEE with 10 uF tantalum + 0.1 uF ceramic caps placed within 5 mm of the supply pins.
This page synthesizes real distributor pricing, drop-in alternatives drawn from the same Maxim MX574A family, and practical design notes not found in the bare manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho MX574ALEWI+CDR — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với MX574ALEWI+CDR (cùng hình factor và footprint) — khác nhau ở Reference Type, Architecture, Conversion Time, Data Interface, Package / Case.
MAX674ALEWI+
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
MAX174AEWI+
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
MX574AJEWI+
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD574AJN
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD574AJDZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →MX574ALEWI+CDR Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bits |
| Architecture | Successive Approximation (SAR) |
| Conversion Time | 25 us (max) |
| Number of Channels | 1 |
| Analog Input Range | 0 to +10 V / 0 to +20 V unipolar; +/-5 V / +/-10 V bipolar |
| Input Voltage Type | Single-Ended |
| Reference Type | Internal (on-chip) |
| Internal Clock | Yes (on-chip oscillator) |
| Output Interface | Parallel (8/16-bit bus, tri-state) |
| Hộp / Vỏ | 28-pin SOIC (Wide, 300-mil SOP) |
| Terminal Form | GULL WING |
| Terminal Count | 28 |
| Temperature Grade | Commercial |
| Nhiệt độ hoạt động | 0C to +70C (commercial grade) |
| Kiểu lắp đặt | Surface Mount |
| Shipping Form | Tape and Reel (CDR suffix) |
Cấu hình chân MX574ALEWI+CDR
| Chân 1 | DB0 — Data output bit 0 (LSB) |
| Chân 2 | DB1 — Data output bit 1 |
| Chân 3 | DB2 — Data output bit 2 |
| Chân 4 | DB3 — Data output bit 3 |
| Chân 5 | DB4 — Data output bit 4 |
| Chân 6 | DB5 — Data output bit 5 |
| Chân 7 | DB6 — Data output bit 6 |
| Chân 8 | DB7 — Data output bit 7 |
| Chân 9 | DB8 — Data output bit 8 |
| Chân 10 | DB9 — Data output bit 9 |
| Chân 11 | DB10 — Data output bit 10 |
| Chân 12 | DB11 — Data output bit 11 (MSB) |
| Chân 13 | STS — Status output (active high during conversion) |
| Chân 14 | NC — Not connected (per datasheet) |
| Chân 15 | CS — Chip Select (active low) |
| Chân 16 | R/C — Read / Convert control |
| Chân 17 | CE — Chip Enable (active high) |
| Chân 18 | VLOGIC — Logic supply (+5 V) |
| Chân 19 | VCC — Positive analog supply (+12 V) |
| Chân 20 | VEE — Negative analog supply (-12 V) |
| Chân 21 | REFOUT — Internal reference output (+10 V nominal) |
| Chân 22 | REFIN — Reference input / sense |
| Chân 23 | BIPOLAR OFFSET — Bipolar offset adjustment |
| Chân 24 | 10 VIN — Analog input (10 V range) |
| Chân 25 | AGND — Analog ground |
| Chân 26 | DGND — Digital ground |
| Chân 27 | RANGE — Range select (10 V / 20 V) |
| Chân 28 | NC — Not connected (per datasheet) |
Ứng dụng tiêu biểu
MX574ALEWI+CDR phù hợp cho 6 Áp dụngs: Industrial Process Control Front-End, Multichannel Data Acquisition Board, Test and Measurement Instrumentation, Digital Panel Meter and HMI Front-End, DSP/Microcontroller Analog Input Module, Audio and Speech Signal Digitization.
Industrial Process Control Front-End
The MX574ALEWI+CDR's +/-10 V bipolar input range and on-chip reference make it a fit for industrial process-control front-ends where 4-20 mA or +/-10 V transducer signals must be digitized with stable offset and gain. Its 25 us conversion (40 kSPS) covers typical multiplexed thermocouple, pressure and strain-gauge channels. The internal clock removes external oscillator parts, and the parallel byte/word bus interfaces directly to a host microcontroller or PLC without glue logic.
Được đề xuất
Multichannel Data Acquisition Board
Plugged behind an analog multiplexer such as an 8/16-channel MUX, the MX574ALEWI+CDR provides deterministic per-channel conversion with no pipeline delay, ideal for scanning data-acquisition cards on ISA, PCI or PC/104 buses. The on-chip reference and oscillator minimize board area and BOM cost, while the parallel interface lets the host CPU burst-read conversions at full 40 kSPS. The 0 to +10 V unipolar range accepts standard signal-conditioning outputs directly.
Được đề xuất
Test and Measurement Instrumentation
Bench-top digital multimeters, chart recorders and portable calibrators benefit from the MX574ALEWI+CDR's 12-bit linearity, internal precision reference and single-chip BOM. The 40 kSPS throughput handles ratiometric measurements and autoranging meter functions without requiring an external sample-hold. The 28-SOIC wide-body package is easy to hand-prototype and the tri-state bus simplifies shared I/O with displays and keypads.
Được đề xuất
Digital Panel Meter and HMI Front-End
Digital panel meters and operator-interface HMI displays digitize 0-10 V or 4-20 mA scaled signals; the MX574ALEWI+CDR's internal reference gives stable gain without calibration drift, and its parallel output drives 7-segment decoder/display drivers directly. The 25 us conversion is fast enough for the update rate of any human-readable display, while the wide-SOIC package eases repair-friendly through-hole-friendly layout for industrial panels.
Được đề xuất
DSP/Microcontroller Analog Input Module
8051, 68HC11, and DSP-based embedded systems gain a true 12-bit analog front-end by adding the MX574ALEWI+CDR to a memory-mapped parallel bus. The device's STAT (status) output provides a hardware handshake so a host CPU can poll conversion-complete without timing loops, while the byte-mode CE/12-8 strap enables 8-bit host processors to read the 12-bit result in two bus cycles. The on-chip reference can drive the host's potentiometric input network directly.
Được đề xuất
Audio and Speech Signal Digitization
Although the MX574ALEWI+CDR is a general-purpose part, its 25 us (40 kSPS) throughput comfortably digitizes speech-band audio up to 20 kHz when paired with an anti-alias filter, and the SAR architecture's zero-latency behavior simplifies event-triggered audio capture. The internal reference and clock allow a compact microphone preamp + ADC BOM, and the parallel interface feeds DMA directly from a host DSP for voice logging or industrial intercom systems.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho MX574ALEWI+CDR — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | MAX674ALEWI+ | MAX174AEWI+ | MX574AJEWI+ | AD574AJN | AD574AJD |
|---|---|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Analog Devices | Analog Devices |
| Package | 28-SOIC (Wide, 300-mil) | 28-SOIC (Wide, 300-mil) | 28-SOIC (Wide, 300-mil) | 28-SOIC (Wide, 300-mil) | 28-PDIP (Wide) | 28-SOIC (Wide, 300-mil) |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Conversion Time (max) | 25 us | 15 us | 8 us | 25 us | 35 us | 35 us |
| Max Throughput | 40 kSPS | 66 kSPS | 125 kSPS | 40 kSPS | ~28 kSPS | ~28 kSPS |
| Internal Reference | Yes (10 V nominal) | Yes (10 V nominal) | Yes (10 V nominal) | Yes (10 V nominal) | Yes (10 V nominal) | Yes (10 V nominal) |
| Analog Input Range | 0-10 V / 0-20 V / +/-5 V / +/-10 V | 0-10 V / 0-20 V / +/-5 V / +/-10 V | 0-10 V / 0-20 V / +/-5 V / +/-10 V | 0-10 V / 0-20 V / +/-5 V / +/-10 V | 0-10 V / 0-20 V / +/-5 V / +/-10 V | 0-10 V / 0-20 V / +/-5 V / +/-10 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Interface | Parallel tri-state (8/16-bit bus) | Parallel tri-state (8/16-bit bus) | Parallel tri-state (8/16-bit bus) | Parallel tri-state (8/16-bit bus) | Parallel tri-state (8/16-bit bus) | Parallel tri-state (8/16-bit bus) |
| Pinout Compatibility | Reference | Drop-in (same die family) | Drop-in (same die family) | Drop-in (same die family) | Drop-in (DIP package) | Drop-in (SOIC package) |
Bảo phân biệt quan trọng
- Complete 12-bit ADC with on-chip reference and clock (vsDiscrete ADC + external reference + external clock)
- Wide bipolar input range directly accepted (vsAD574AJN / AD574AJD)
- Parallel byte/word interface selectable via CE/12-8 strap (vsSerial-interface ADCs (e.g. AD7888))
Ghi chú thiết kế
The MX574ALEWI+CDR requires three supplies: +12 V (VCC pin 19), -12 V (VEE pin 20) and +5 V (VLOGIC pin 18). Decouple each supply pin with a 10 uF tantalum bulk capacitor plus a 0.1 uF ceramic placed within 5 mm of the pin; the +5 V logic rail and +12 V analog rail should be filtered separately to prevent digital switching noise from coupling into the analog reference. According to the family datasheet, supply current is typically 8 mA on +12 V and +5 V and 1 mA on -12 V, so a small linear regulator is sufficient.
A common pitfall is leaving the analog input floating when the device is idle; the internal DAC switching injects charge that can couple into the input if it is not DC-biased. Tie the input to ground through 1 kohm if unused. Do not exceed the analog input range on the 10 V pin; the 10 V pin's maximum is +/-15 V with the 10 V range strap and +/-25 V on the 20 V range pin. Pin 23 (BIPOLAR OFFSET) should be tied to REFOUT through 50 ohm in unipolar mode to avoid offset drift.
Layout tip: place the analog ground plane under the analog pins (1-12, 19-27) and the digital ground plane under the digital pins (13-18, 28), joining them at a single point under pin 25 (AGND). Keep the REFOUT track short and guard with analog ground on both sides to prevent noise pickup. Use a 4-layer stackup with VCC and VEE power planes on the inner layers to keep analog input traces over a continuous ground plane and minimize cross-coupling from parallel data bus edges.
Estimated: at 40 kSPS conversion rate, the parallel data bus (DB0-DB11) toggles up to 480k transitions/sec; route these lines away from the analog input and reference traces and add 47 ohm source-series termination on the DB lines if the host is more than 50 mm away. The STS (status, pin 13) output rising edge is the conversion-complete signal that triggers the host's parallel read; treat this as an asynchronous interrupt and synchronize it through one flip-flop on the host side to avoid metastability.
Thông tin tuân thủ
RoHS compliant per Maxim Integrated product family datasheet (EWI suffix indicates lead-free matte-tin finish). Not AEC-Q100 qualified - choose MAX574A or industrial screening options for automotive. Halogen-free status not explicitly stated in the datasheet excerpts and is therefore 'unknown' per the data authenticity rules.
