10AS032E4F27I3LG vs 10AS032E3F29I2SG 比較
詳細並排比較 10AS032E4F27I3LG 由 Intel 與 10AS032E3F29I2SG 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 10AS032E4F27I3LG | 10AS032E3F29I2SG |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 320,000 | 320,000 |
| Hard Processor Subsystem (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Clock Frequency | 1.5 GHz | — |
| Speed Grade | E4 (-4, mid-tier) | — |
| Temperature Grade | Industrial (-40C to +100C) | — |
| 封裝 | 672-pin FCBGA (F27, 27x27 mm) | 780-pin FC-FBGA (F29), 29 x 29 mm |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| MSL 等級 | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | [DATA_NEEDED: MSL rating] |
| Process Technology | 20 nm | 20 nm |
| Transceivers | Up to 24 channels, up to 14.1 Gbps (family-level) | — |
| DSP Blocks | Hardened floating-point DSP (family-level) | — |
| Memory Interfaces | DDR3 / DDR4 with hard controllers (family-level) | — |
| Configuration Method | JTAG, ASx4, FPP (family-level) | — |
| Device Variant | — | 10AS032 |
| Hard Processor System (HPS) | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Core Logic Voltage | — | 0.9 V |
| 工作溫度 | — | -40C to +100C (Industrial) |
| Configuration | — | JTAG / Active Serial (AS) via Quartus Prime |
| Ordering Code Speed Grade | — | E3 (transceiver / logic speed grade) |
| On-chip Transceivers | — | [DATA_NEEDED: transceiver count and max data rate] |