10AS032H2F34E2LG vs 10AS032H1F35E1HG 比較
詳細並排比較 10AS032H2F34E2LG 由 Intel 與 10AS032H1F35E1HG 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 10AS032H2F34E2LG | 10AS032H1F35E1HG |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Arria 10 SX | — |
| Device Tier | 10AS032 (mid-density) | — |
| Configuration | SoC FPGA (HPS + FPGA fabric) | — |
| Logic Elements | 320,000 | 320K |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Operating Frequency | 1.5 GHz | — |
| 封裝 | 1152-ball FC-FBGA (F34), 35 x 35 mm | 1152-FBGA, FC (Flip-Chip BGA), 35x35 mm |
| Speed Grade | 2 | — |
| Temperature Grade | E2 (commercial/extended) | — |
| On-chip Memory (M20K blocks) | Approx. 21 Mb [DATA_NEEDED: exact Mb from datasheet] | — |
| DSP Blocks | Variable-precision, IEEE 754 single-precision FP support | Variable-precision DSP blocks |
| Transceivers | Up to 14.1 Gbps [DATA_NEEDED: exact count for F34 package] | Multi-gigabit transceivers (up to 24 channels, family-wide) |
| Memory Controller Hard IP | DDR4, DDR3, QDRII+, RLDRAM3 | — |
| Process Node | 20 nm | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS 狀態 | Compliant | Compliant |
| Form of Terminal | Ball (BGA) | — |
| Terminal Pitch | 1 mm | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | Arria 10 SX |
| Device Type | — | System on Chip (SoC) FPGA |
| Hard Processor Subsystem (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 1.5 GHz |
| User I/O Count | — | 384 |
| Process Technology | — | 20nm TSMC |
| Embedded Memory | — | M20K blocks (variable, density per family) |
| External Memory Interfaces | — | DDR4, DDR3, RLDRAM3, QDRII+ |
| Hard Memory Controller | — | Yes |
| Hard PCIe | — | PCI Express Gen3 controllers (hard IP) |
| Partial Reconfiguration | — | Supported |
| 工作溫度 | — | Industrial / Extended grade (per part suffix) |
| Lead-Free | — | Yes |