10AS048H2F34E1HG vs 10AS048K1F35E1HG 比較

詳細並排比較 10AS048H2F34E1HG 由 Altera 與 10AS048K1F35E1HG 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 10AS048H2F34E1HG 10AS048K1F35E1HG
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Arria 10 SX SoC FPGA —
Logic Elements 480K 480,000
Hard Processor System Dual ARM Cortex-A9 MPCore with CoreSight Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Frequency 1.5 GHz —
封裝 1152-ball FCBGA (F34), 35x35 mm 1152-ball FC-BGA (flip-chip), 35x35 mm
Speed Grade H2 —
Transceivers Multi-gigabit (14.1 Gbps-capable, family-level) Multi-gigabit serial transceivers, up to 17.4 Gbps (family)
DSP Blocks Variable-precision DSP (family-level) Variable-precision DSP blocks (per family)
On-chip Memory M20K blocks plus MLAB (family-level) —
Memory Interface DDR3/DDR4 hard memory controllers (family-level) —
PCIe Hard IP Gen2/Gen3 capable (family-level) —
工作溫度 Extended (per OPN E1 suffix, family-level) Industrial / commercial per part number suffix
安裝類型 Surface Mount (BGA) Surface Mount
RoHS 狀態 Compliant (per distributor listing) Compliant
Configuration Device Supported (family-level, external or internal) —
Product Series — Arria 10 SX SoC FPGA
HPS Clock Speed — Up to 1.5 GHz
Process Technology — 20 nm
Memory Interfaces — DDR4, DDR3, LPDDR3, QDR IV (hard controllers)
On-chip RAM — M20K memory blocks + MLAB (per family)
HPS Peripherals — Gigabit Ethernet, USB 2.0 OTG, SD/SDIO/MMC, SPI, I2C, UART, CAN
Hard IP Blocks — PCIe Gen3 (hard), 10/40 GbE MAC, DDR controllers, partial reconfiguration
Configuration — FPGA fabric + HPS independent configuration, supports AS/PS/JTAG
REACH Status — [DATA_NEEDED: REACH compliance]
Design Software — Intel Quartus Prime (legacy: Altera Quartus II)

資料表與資源

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