10AS057K2F35E2LG vs 10AS057K2F35I2SG 比較
詳細並排比較 10AS057K2F35E2LG 由 Intel 與 10AS057K2F35I2SG 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 10AS057K2F35E2LG | 10AS057K2F35I2SG |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570K |
| Process Node | TSMC 20 nm | 20 nm TSMC |
| HPS Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 1.5 GHz | — |
| DSP Blocks | [DATA_NEEDED: 18x19 multiplier count] | [DATA_NEEDED: DSP block count] |
| Embedded Memory (M20K) | [DATA_NEEDED: M20K block count and total bits] | — |
| Transceivers | Up to 24 channels, up to 17.4 Gbps | [DATA_NEEDED: transceiver count and max data rate] |
| PCIe Hard IP | Gen3 x4 (rootport/endpoint) | — |
| User I/Os | 396 | — |
| 封裝 | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch | 1152-ball FC-FBGA (F35), 35x35 mm |
| Speed Grade | E2 (commercial/extended) | -2 |
| 工作溫度 | -40C to +100C (extended-industrial screening) | -40C to +100C (Industrial) |
| Configuration | SRAM-based, partial reconfiguration, SEU mitigation, ECC | FPGA + HPS independent / coordinated boot |
| Memory Interfaces | DDR3/DDR4 with hard PHY (HPS + FPGA) | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| RoHS 狀態 | Compliant | Compliant (lead-free finish) |
| Lead-Free | Yes | — |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| User I/O Count | — | 396 (per Heisener parametric data) |
| Embedded Memory | — | [DATA_NEEDED: M20K / MLAB bit count] |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| 安裝類型 | — | Surface Mount (BGA) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |