10CL055YF484C8G vs 10CL055YU484C6G 比較

詳細並排比較 10CL055YF484C8G 由 Intel 與 10CL055YU484C6G 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 10CL055YF484C8G 10CL055YU484C6G
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements 55,856 —
Embedded Memory 2,396,160 bits —
Maximum User I/O 321 —
DSP Blocks (18x18 Multipliers) 156 —
PLLs 4 4
Memory Blocks 56 M9K —
封裝 484-FBGA (F484) 484-pin UBGA (19 mm x 19 mm)
Operating Temperature Grade Commercial (0 C to 85 C) —
Core Voltage 1.0 V 1.0 V (typical)
I/O Bank Voltages 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Process Technology 60 nm low-power CMOS TSMC 60 nm low-power
Configuration FPGA (SRAM-based, volatile) —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 Compliant Compliant
MSL 等級 3 (168 hours) [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Logic Elements (LE) — 55,856
Embedded Memory Bits — 2,396,160 bits (approximately 2.5 Mb)
Maximum User I/Os — 321
Embedded 18x18 Multipliers — 156
Global Clocks — 20
I/O Voltage Standards — LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V)
Speed Grade — 6 (commercial, slowest in family)
工作溫度 — 0 C to +85 C (commercial, C suffix)
Lead-Free / Halogen-Free — Yes / [DATA_NEEDED: halogen-free status]
Configuration Modes — Active Serial (AS), Passive Serial (PS), JTAG
Transceivers — None (Cyclone 10 LP family does not include SERDES)
Hard Memory Controller — Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP)

資料表與資源

瀏覽所有產品 建立 BOM 索取報價