10CL055YU484C6G vs 10CL040YU484C6G 比較
詳細並排比較 10CL055YU484C6G 由 Altera 與 10CL040YU484C6G 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 10CL055YU484C6G | 10CL040YU484C6G |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Cyclone 10 LP | Cyclone 10 LP |
| Logic Elements (LE) | 55,856 | 39,600 |
| Embedded Memory Bits | 2,396,160 bits (approximately 2.5 Mb) | — |
| Maximum User I/Os | 321 | — |
| Embedded 18x18 Multipliers | 156 | — |
| PLLs | 4 | 4 |
| Global Clocks | 20 | — |
| Core Voltage | 1.0 V (typical) | — |
| I/O Voltage Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) | — |
| Speed Grade | 6 (commercial, slowest in family) | 6 (C6G) |
| 封裝 | 484-pin UBGA (19 mm x 19 mm) | 484-FBGA (UBGA-484), 1.0 mm pitch |
| Process Technology | TSMC 60 nm low-power | 60 nm low-power CMOS |
| 工作溫度 | 0 C to +85 C (commercial, C suffix) | 0C to +85C (commercial) |
| 安裝類型 | Surface Mount | — |
| MSL 等級 | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | 3 (168 hours) |
| RoHS 狀態 | Compliant | Compliant |
| Lead-Free / Halogen-Free | Yes / [DATA_NEEDED: halogen-free status] | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Transceivers | None (Cyclone 10 LP family does not include SERDES) | — |
| Hard Memory Controller | Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) | — |
| Series | — | Cyclone 10 LP |
| Configurable Logic Blocks (CLB) | — | 2,475 |
| Embedded Memory (bits) | — | 1,161,216 |
| Memory Blocks (M9K) | — | 66 |
| 18x18 Multipliers | — | 156 |
| Maximum User I/O | — | 233 |
| I/O Banks | — | 8 |
| Configuration Mode | — | JTAG (IEEE 1149.1), Active Serial (AS), Passive Serial (PS) |
| Supply Voltage (Core) | — | [DATA_NEEDED: Vcore] |
| Lead-Free | — | Yes |
| Packaging Type | — | Tray |