10M08DFV81C8G vs 10M08DCV81I7G 比較

詳細並排比較 10M08DFV81C8G 由 Altera 與 10M08DCV81I7G 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 10M08DFV81C8G 10M08DCV81I7G
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Series MAX 10 —
Logic Elements 8,000 —
Embedded Memory (User Flash) 387,072 bits —
Total RAM Bits 378 Kbits —
Number of Logic Array Blocks (LABs) 500 —
Number of I/O 56 —
Embedded 18x18 Multipliers 56 —
Technology 55 nm embedded flash CMOS —
Core Voltage 1.2 V —
工作溫度 0C to +85C (Commercial) Industrial -40C to +100C (I7 grade)
Speed Grade 8 —
封裝 81-ball WLCSP (V81) —
安裝類型 Surface Mount (Wafer Level Chip Scale) Surface Mount (WLCSP - requires underfill)
Configuration Memory Internal (instant-on, no external flash required) On-chip dual-configuration flash, instant-on
RoHS 狀態 Compliant Compliant
Product Family — MAX 10
Logic Elements (LE) — 8000
Embedded User Flash — 387072 bit (378 Kbit)
Maximum User I/Os — 56
Package Type — 81-ball WLCSP (UFBGA, wafer-level chip-scale package)
Process Node — [DATA_NEEDED: process node]
Embedded ADC — 12-bit SAR ADC (1 Msps) [DATA_NEEDED: number of channels]
Supply Voltage Core — [DATA_NEEDED: VCC core voltage]
I/O Bank Count — [DATA_NEEDED: number of I/O banks]
I/O Standards Supported — LVCMOS, LVTTL, LVDS, SSTL, RSDS
Memory Interfaces — DDR3, DDR3L, LPDDR2 (external PHY required)
PLL Count — [DATA_NEEDED: number of PLLs]
Global Clock Networks — [DATA_NEEDED: clock network count]
Configuration Modes — JTAG, Active Serial (AS), Passive Serial (PS)
MSL 等級 — [DATA_NEEDED: MSL rating]
Design Software — Intel Quartus Prime (MAX 10 device support)

資料表與資源

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