5CSEBA4U19I7SN vs 5CSEBA6U19I7SN 比較
詳細並排比較 5CSEBA4U19I7SN 由 Intel 與 5CSEBA6U19I7SN 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5CSEBA4U19I7SN | 5CSEBA6U19I7SN |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | Cyclone V SE SoC FPGA | — |
| Device Family | Cyclone V | — |
| Logic Elements | 40,000 | — |
| Hard Processor System (HPS) | Single ARM Cortex-A9 MPCore with CoreSight | Single-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 800 MHz | 800 MHz |
| 封裝 | 484-pin UBG A (19x19 mm) | 484-pin UBGA (19x19 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -40C to +100C (Industrial) | Industrial grade (I) -40C to +100C junction |
| Process Node | 28 nm low-power | — |
| Supply Voltage (Core) | 1.1 V (typical) | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) | — |
| Embedded Memory | [DATA_NEEDED: total Kbits of M9K blocks] | — |
| 18x18 Hardware Multipliers | [DATA_NEEDED: count] | — |
| PLLs | [DATA_NEEDED: count] | Integrated phase-locked loops |
| Transceivers | Not applicable (SE family, transceiver-less) | — |
| PCI Express Hard IP | Gen1 capable (rootport/endpoint) | — |
| DDR Memory Support | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric | — |
| RoHS 狀態 | Compliant | Compliant |
| Family | — | Cyclone V SE SoC FPGA |
| Logic Elements (LEs) | — | 110,000 |
| Logic Array Blocks (LABs) | — | 4150 |
| Maximum User I/Os | — | 66 |
| On-chip Memory | — | 64 KB |
| DSP Blocks | — | Variable-precision DSP blocks |
| External Memory Support | — | DDR3, DDR3L, LPDDR2 (via HPS) |
| Process Technology | — | 28 nm low-power (TSMC) |
| Lead Free | — | Yes |
| Ordering Part Number | — | 5CSEBA6U19I7SN |