5CSEBA5U19I7SN vs 5CSEBA6U19C7SN 比較
詳細並排比較 5CSEBA5U19I7SN 由 Altera 與 5CSEBA6U19C7SN 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5CSEBA5U19I7SN | 5CSEBA6U19C7SN |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Cyclone V SE SoC FPGA | 5CSEBA6 (Cyclone V SE, 110K LE) |
| Device Variant | 5CSEA5 | — |
| Logic Elements | 85K | 110,000 |
| Hard Processor System | Single-core ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock | 800 MHz | — |
| FPGA Fabric Maximum Clock | [DATA_NEEDED: maximum fabric frequency] | — |
| 封裝 | 484-pin UBG (Ultra FineLine BGA, 19x19 mm) | — |
| Package Designator | U19 | — |
| Speed/Logic Grade | A5 (mid-tier speed grade) | — |
| User I/O Count | 66 (per distributor listing); up to 288 in Cyclone V SE family typical | — |
| Embedded Memory | [DATA_NEEDED: total Kbits] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count for 5CSEA5] | Variable-precision DSP blocks (Cyclone V architecture) |
| PLL Count | [DATA_NEEDED: PLL count for 5CSEA5] | — |
| Transceivers | [DATA_NEEDED: transceiver count for 5CSEA5 U19] | Not enabled on this SE variant |
| 工作接面溫度 | -40C to +100C (industrial) | — |
| Process Technology | TSMC 28 nm low-power | — |
| Configuration | SRAM-based, volatile | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS 狀態 | Compliant | Compliant |
| MSL 等級 | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | Cyclone V SE SoC FPGA |
| HPS Maximum Clock Frequency | — | 800 MHz |
| User I/O Pins | — | 66 (FPGA fabric, per distributor listing) |
| Total Package Pins | — | 484 |
| Package Type | — | 484-UBGA (Ultra BGA), 19x19 mm |
| 工作溫度 | — | Industrial grade (per part number code) |
| Lead-Free | — | Yes |
| FPGA Process Node | — | Low-power TSMC process |
| On-Chip Memory | — | Embedded SRAM (FPGA fabric) |