5M1270ZF256I5N vs 5M1270ZF324I5N 比較
詳細並排比較 5M1270ZF256I5N 由 Altera 與 5M1270ZF324I5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5M1270ZF256I5N | 5M1270ZF324I5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX V | — |
| Macro Cells | 980 | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| User I/O Pins (max) | 212 | — |
| 封裝 | 256-ball FBGA | 324-pin FBGA (FineLine BGA), 19 mm |
| Configuration Memory | Non-volatile flash (instant-on) | — |
| Programming Interface | JTAG, Active Serial, Active Parallel | — |
| Process Technology | 0.18 um CMOS | — |
| Typical Quiescent Power | [DATA_NEEDED: typical quiescent power in mW] | — |
| 工作溫度 | -40C to +100C (Industrial) | -40 °C to +100 °C (TJ) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | Yes |
| Series | — | MAX V |
| Device Family | — | 5M1270Z |
| Number of Macrocells | — | 980 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 271 |
| Maximum Internal Frequency | — | 212 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 6.2 ns |
| Number of I/O Banks | — | 8 |
| Core Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage Standards Supported | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (LVCMOS, LVTTL, SSTL) |
| Programmable Logic Type | — | In-System Programmable (ISP) flash-based CPLD |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| On-Chip User Flash Memory | — | 8 Kbits |
| 安裝類型 | — | Surface Mount |
| Standby Current (typ, 25 °C) | — | 40 µA |
| RoHS Compliance | — | Compliant |