5M1270ZT144C5N vs 5M1270ZT144A5N 比較
詳細並排比較 5M1270ZT144C5N 由 Altera 與 5M1270ZT144A5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ 啟用中
規格比較
| 參數 | 5M1270ZT144C5N | 5M1270ZT144A5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 單價 (USD) | — | $19.85 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Series | MAX V | — |
| Logic Elements | 1270 | 2120 (approx.) |
| Macrocells | 980 | — |
| User I/Os | 114 | 114 |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | Flash (non-volatile, in-system programmable) | — |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | JTAG (IEEE 1149.1) |
| Program/Erase Cycles | Up to 100,000 | — |
| 封裝 | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | TQFP-144 (T144) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 C to +85 C (commercial grade) | -40C to +125C (automotive) |
| RoHS 狀態 | Compliant | Compliant |
| Family | — | MAX V |
| Macro Cells | — | 980 |
| User Flash Memory | — | 8 Kbits |
| Maximum Operating Frequency | — | 201.1 MHz |
| Speed Grade | — | 5N |
| Core Supply Voltage | — | 1.8 V |
| I/O Bank Voltage Support | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Process Technology | — | Non-volatile flash CMOS |
| Design Software | — | Quartus II / Quartus Prime |
| Automotive Qualification | — | AEC-Q100 |
| Internal Features | — | Pull-up resistors, bus-hold, on-chip oscillator |