A42MX24-2PLG84I vs A42MX24-1PLG84I 比較
詳細並排比較 A42MX24-2PLG84I 由 Microchip Technology 與 A42MX24-1PLG84I 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ 啟用中Microchip Technology
A42MX24-1PLG84I - 36K Gate MX FPGA, PLCC-84 | Microchip
A42MX24-1PLG84I ⚠ 最後購買機會規格比較
| 參數 | A42MX24-2PLG84I | A42MX24-1PLG84I |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Family | MX (42MX) | MX (42MX) |
| System Gates | 36000 gates | 36000 |
| Logic Cells | 912 cells | — |
| User I/O | 72 | — |
| Technology | 0.45 um antifuse | — |
| Core Architecture Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V / 5.0 V mixed | — |
| Speed Grade | -2 | -1 |
| Programmability | One-Time Programmable (antifuse) | — |
| 工作溫度 | -40C to +85C (Industrial) | -40C to +85C |
| 封裝 | 84-PLCC (J-Lead) | 84-LCC (J-Lead, PLCC-84) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration | No external boot device required | — |
| Dedicated Decode Blocks | D-modules (wide-input AND, CPLD-like) | — |
| RoHS 狀態 | Lead Free (per Kynix listing) | ROHS3 Compliant |
| Packaging | Tray | Tray |
| Primary Applications | ASIC alternative, legacy PLD integration | — |
| Logic Cells / Logic Blocks | — | 912 |
| Process Technology | — | 0.45 um CMOS |
| 供應電壓 | — | 3V ~ 3.6V, 4.5V ~ 5.5V |
| I/O Count (this package) | — | 72 |
| Max User I/O (family) | — | 202 |
| Dual-Port SRAM | — | 2.5 kbits |
| Logic Family | — | CMOS |
| Manufacturer Lead Time | — | 10 weeks |
| Product Status | — | Last Time Buy |