ATF22V10C-7JC vs ATF22V10C-5JC 比較
詳細並排比較 ATF22V10C-7JC 由 Microchip Technology 與 ATF22V10C-5JC 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
ATF22V10C-7JC - 500-Gate 7 ns EE PLD | Microchip Technology
ATF22V10C-7JC UnknownMicrochip Technology
ATF22V10C-5JC - 500-Gate EE PLD, 10 Macrocells, 5ns | Microchip
ATF22V10C-5JC ✓ 啟用中規格比較
| 參數 | ATF22V10C-7JC | ATF22V10C-5JC |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | Logic ICs | Logic ICs |
| 生命週期狀態 | Unknown | 啟用中 |
| Device Type | 22V10-series electrically erasable programmable logic device | EE PLD (Electrically Erasable Programmable Logic Device) |
| Programmable Logic Type | EEPLD | — |
| Logic Density | 500 gates | — |
| Macrocells | 10 macrocells | 10 macrocells |
| 供應電壓 | 5 V | 5 V nominal |
| Speed Grade | 7 ns | — |
| Reported Propagation Delay | 7.5 ns | — |
| 封裝 | 28-pin PLCC | 28-PLCC (QCCJ), J-lead, 11.51 mm x 11.51 mm |
| Package Body Size | 11.51 mm x 11.51 mm | — |
| 安裝類型 | Surface mount | Surface Mount |
| Technology | CMOS electrically erasable flash-memory technology | CMOS with electrically erasable Flash configuration memory |
| Power-Down Control | Optional pin-controlled power-down; PLCC pin 5 | — |
| Temperature Grade | Industrial temperature | Commercial |
| Supported Fusemap | JEDEC 22V10 fusemap compatible | — |
| Family Maximum Speed | Down to 5 ns | — |
| Family Typical Power Dissipation | As low as 100 uA | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance statement] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | ATF22V10C / 22V10 |
| Total Gates | — | 500 gates |
| Propagation Delay (tPD) | — | 5 ns (min, -5 speed grade) |
| Max Frequency | — | 166 MHz (per FindIC listing of device attributes) |
| Supply Tolerance (Commercial) | — | 5 V +/- 5% |
| Supply Tolerance (Military/Industrial) | — | 5 V +/- 10% |
| Power-Down Current | — | 10 uA (typical) |
| Input Latch Feature | — | Yes - holds inputs to previous logic states |
| Fusemap Compatibility | — | JEDEC GAL22V10 fusemap compatible (pin-to-pin) |
| Package Code | — | QCCJ |
| Terminals | — | 28 J-bend (J-lead) terminals |
| Package Shape | — | Square |
| Programmable | — | Yes - in-circuit electrically erasable |
| Datasheet Document | — | ATF22V10C(Q) Complete Datasheet (Microchip doc0735 PDF) |