CDK1308AILP40 vs CDK1307CILP40 比較

詳細並排比較 CDK1308AILP40 由 MaxLinear 與 CDK1307CILP40 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

MaxLinear
CDK1307CILP40 CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 ✓ 啟用中

規格比較

參數 CDK1308AILP40 CDK1307CILP40
品牌 MaxLinear MaxLinear
類別 ADC/DAC ADC/DAC
生命週期狀態 啟用中 啟用中
解析度 10 bit 12-bit / 13-bit selectable
Maximum Sample Rate 20 MSPS —
Family Sample Rate Options 20 / 40 / 65 / 80 MSPS —
Architecture Proprietary, digital error correction Multi-stage pipeline with digital error correction
Reference Internal (no external reference required) Internal (1.2 V bandgap)
Digital Interface CMOS, parallel —
Control Interface CMOS CMOS serial configuration
Power-Down Pin (PD_N) Yes (active low) —
Sleep Pin (SLP_N) Yes (active low) —
封裝 40-pin QFN 40-pin LQFP (LP)
安裝類型 Surface Mount —
Power Consumption Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) —
工作溫度範圍 [DATA_NEEDED: operating temperature range] —
供應電壓 [DATA_NEEDED: AVDD / DRVDD values] —
RoHS 狀態 Compliant (per distributor listings) Compliant
Manufacturer MaxLinear (formerly Exar Corporation) MaxLinear (formerly Exar/Cadeka)
Part Number — CDK1307CILP40
功能 — Analog-to-Digital Converter (ADC)
Sample Rate — 65 MSPS (family supports 20/40/65/80 MSPS)
Input Type — Single-ended analog input
Full-Scale Input Range — 1 Vpp typical
Supply Voltage (Analog) — 3.3 V
Supply Voltage (Digital) — 3.3 V
Output Interface — Parallel CMOS
工作溫度 — -40 C to +85 C (industrial)

資料表與資源

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