CDK2307AILP64 vs CDK2307CILP64 比較

詳細並排比較 CDK2307AILP64 由 Cadeka 與 CDK2307CILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

MaxLinear
CDK2307CILP64 CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear

CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear

CDK2307CILP64 ✓ 啟用中

規格比較

參數 CDK2307AILP64 CDK2307CILP64
品牌 Cadeka MaxLinear
類別 ADC/DAC ADC/DAC
生命週期狀態 啟用中 啟用中
Manufacturer Cadeka Microcircuits (MaxLinear) MaxLinear (formerly Exar / Cadeka)
Part Number CDK2307AILP64 CDK2307CILP64
Description Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter —
解析度 13 bit (12-bit option via CDK2308 family) 12-bit / 13-bit
Sampling Rate (this variant) 20 MSPS —
Sampling Rate (family max) 80 MSPS (CDK2307AILP64 = 20 MSPS grade) —
Number of Channels 2 (dual, simultaneous sampling) 2
Input Type Single-ended analog input Differential analog inputs
Output Interface Parallel CMOS —
Core Supply Voltage 1.8 V —
I/O Supply Voltage 1.7 V to 3.6 V —
Power Dissipation 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS —
Reference Internal (bandgap, integrated) —
封裝 64-pin QFN (LP64) with exposed pad, 9x9 mm 64-pin QFN (LP64) with exposed pad
安裝類型 Surface Mount Surface Mount
工作溫度 -40C to +85C (industrial) [DATA_NEEDED: exact temp grade] —
Pin Compatibility Pin-compatible with CDK2308 family (12-bit variant) —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
功能 — Dual-channel Analog-to-Digital Converter (ADC)
Maximum Sample Rate — 80 MSPS (12-bit), 65 MSPS (13-bit)
Supported Sample Rates — 20 / 40 / 65 / 80 MSPS
Converter Architecture — Pipelined with digital error correction
Digital Output — Parallel CMOS
Data Interface — CMOS parallel
Reference Type — Internal (on-chip)
Packaging — Tray
工作溫度範圍 — [DATA_NEEDED: operating temperature range]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價