CDK2308BILP64 vs CDK2308CILP64 比較

詳細並排比較 CDK2308BILP64 由 MaxLinear 與 CDK2308CILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

MaxLinear
CDK2308BILP64 CDK2308BILP64 - Dual 10-bit 40MSPS ADC | MaxLinear (Cadeka)

CDK2308BILP64 - Dual 10-bit 40MSPS ADC | MaxLinear (Cadeka)

CDK2308BILP64 ✓ 啟用中

規格比較

參數 CDK2308BILP64 CDK2308CILP64
品牌 MaxLinear MaxLinear
類別 ADC/DAC ADC/DAC
生命週期狀態 啟用中 啟用中
解析度 10 bit 10 bit
Number of Channels 2 (dual) 2 (dual)
Sample Rate (B grade) 40 MSPS per channel —
Family Speed Grades 20 / 40 / 65 / 80 MSPS (A/B/C/D grades) —
Architecture Pipelined with on-chip track-and-hold Pipelined
Input Bandwidth Up to 100 MHz IF (full-power) —
Input Type Differential analog input Differential, single-ended capable
供應電壓 3.3 V (analog and digital) —
Power Consumption [DATA_NEEDED: total power at 40 MSPS] —
Power-Down Modes Per-channel, standby, full power-down —
Output Interface Parallel CMOS —
封裝 64-pin QFN (LP), 9x9 mm with exposed pad 64-pin QFN with Exposed Pad (EP)
工作溫度範圍 [DATA_NEEDED: industrial / extended range] —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 Compliant Compliant
Lead-Free Yes —
Datasheet Document Cadeka / Exar CDK2308 family datasheet (15 pages) —
Sample Rate (max) — 65 MSPS per channel
Analog Supply Voltage — 3.3 V
Digital Output Supply — 1.8 V to 3.3 V
Digital Output Interface — Parallel CMOS
Data Rate (per channel) — Up to 65 MSPS
Reference — Internal bandgap; external reference supported
Sample-Rate Family — 20 / 40 / 65 / 80 MSPS (per datasheet family)
工作溫度 — -40 C to +85 C (industrial)

資料表與資源

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