CDK2308DILP64 vs CDK2308CILP64 比較
詳細並排比較 CDK2308DILP64 由 MaxLinear 與 CDK2308CILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK2308DILP64 | CDK2308CILP64 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 解析度 | 10 bit | 10 bit |
| Number of Channels | 2 (Dual) | 2 (dual) |
| Sampling Rate (max) | 80 MSPS | — |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS (programmable) | — |
| Architecture | Pipelined ADC | Pipelined |
| Input Type | Single-ended analog | Differential, single-ended capable |
| Power Dissipation | 78 mW per channel at 80 MSPS | — |
| Supply Voltage (AVDD) | [DATA_NEEDED: AVDD nominal voltage] | — |
| Supply Voltage (DRVDD) | [DATA_NEEDED: DRVDD nominal voltage] | — |
| Input Bandwidth | [DATA_NEEDED: -3 dB input bandwidth] | — |
| SNR | [DATA_NEEDED: SNR at full scale] | — |
| SFDR | [DATA_NEEDED: SFDR] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| 封裝 | 64-QFN (9x9 mm) | 64-pin QFN with Exposed Pad (EP) |
| 工作溫度範圍 | -40 C to +85 C | — |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | Compliant | Compliant |
| Power-Down Modes | Per-channel standby, chip standby, full power-down | — |
| Track-and-Hold Amplifier | Integrated, optimized for IF frequencies | — |
| Sample Rate (max) | — | 65 MSPS per channel |
| Analog Supply Voltage | — | 3.3 V |
| Digital Output Supply | — | 1.8 V to 3.3 V |
| Digital Output Interface | — | Parallel CMOS |
| Data Rate (per channel) | — | Up to 65 MSPS |
| Reference | — | Internal bandgap; external reference supported |
| Sample-Rate Family | — | 20 / 40 / 65 / 80 MSPS (per datasheet family) |
| 工作溫度 | — | -40 C to +85 C (industrial) |