CDK8307BILP64 vs CDK8307CILP64 比較
詳細並排比較 CDK8307BILP64 由 MaxLinear 與 CDK8307CILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK8307BILP64 | CDK8307CILP64 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Product Type | Octal Analog-to-Digital Converter (ADC) | — |
| 解析度 | 12-bit or 13-bit (programmable) | 12/13-bit (selectable) |
| Sample Rate (per channel) | 20 / 40 / 50 / 65 MSPS | — |
| Number of Channels | 8 | 8 (simultaneous sampling) |
| Total Power Dissipation | 280 mW | — |
| Data Output Interface | Serial LVDS | — |
| Input Type | Differential analog inputs (one per channel) | Differential analog inputs |
| Reference | Internal (integrated bandgap reference) | Internal (integrated bandgap) |
| Clock Architecture | External reference clock with integrated PLL (x12 or x14 multiplication) | — |
| Control Interface | Serial control interface | SPI-compatible serial |
| 封裝 | 64-pin QFN (LP suffix) | 64-pin LQFP (LP64) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | [DATA_NEEDED: supply voltage rating] | — |
| RoHS 狀態 | Compliant | Compliant (per MaxLinear product page) |
| Sample Rate | — | 65 MSPS maximum (20/40/50/65 MSPS grades) |
| Digital Output Interface | — | Serial LVDS |
| Architecture | — | Proprietary pipeline ADC |
| Power Profile | — | Ultra-low power (per-channel) |
| Supply Voltage (AVDD) | — | [DATA_NEEDED: AVDD nominal] |
| Supply Voltage (DRVDD/LVDS) | — | [DATA_NEEDED: DRVDD nominal] |
| ENOB | — | [DATA_NEEDED: effective number of bits] |
| SNR | — | [DATA_NEEDED: signal-to-noise ratio] |
| SFDR | — | [DATA_NEEDED: spurious-free dynamic range] |