EP1810GM883B vs EP1810GI-45 比較
詳細並排比較 EP1810GM883B 由 Altera 與 EP1810GI-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883B | EP1810GI-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 24 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS |
| 工作溫度 | -55 °C to +125 °C (Military, MIL-STD-883B) | [DATA_NEEDED: operating temperature range] |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | Ceramic Pin Grid Array with UV window |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| 安裝類型 | Through-hole (PGA socket or PCB through-hole) | Through-Hole |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| 腳位數 | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| RoHS 狀態 | — | Non-compliant (ceramic PGA) |
| Lead-Free | — | No |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |