EP1810JC-45 vs EP1810JM-45 比較
詳細並排比較 EP1810JC-45 由 Altera 與 EP1810JM-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-45 | EP1810JM-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns (max, -45 speed grade) |
| 最大時脈頻率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS, UV-EPROM configuration |
| Maximum Supply Voltage | 5.25 V | — |
| 封裝 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| 腳位數 | 68 | 68 |
| Package Code | QCCJ | JM (windowed ceramic, UV-erasable) |
| Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount | Surface Mount (J-lead) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Device Family | — | Classic EPLD (EP1810 series) |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Package Type | — | JLCC-68 (ceramic J-leaded chip carrier) |
| 工作溫度 | — | -55 C to +125 C (military grade) |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |