EP1810LC-25 vs EP1810LC-35 比較
詳細並排比較 EP1810LC-25 由 Altera 與 EP1810LC-35 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最後購買機會規格比較
| 參數 | EP1810LC-25 | EP1810LC-35 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | [DATA_NEEDED: I/O count exact] |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | 5 V (4.75 V to 5.25 V) |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| 封裝 | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (J-Lead) |
| Package Code | LC = 68-pin JLCC | — |
| 安裝類型 | Surface Mount | Surface Mount (socketable) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable EPROM |
| Programmable Interconnect | Global + Local buses | Centralized Programmable Interconnect Array (PIA) |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| 生命週期狀態 | Obsolete (legacy Altera Classic family) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED] |
| 工作溫度 | [DATA_NEEDED: temperature grade for LC package] | 0C to +70C (commercial) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | Classic EP1810 |
| Equivalent Gates | — | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | — | 28.6 MHz |
| Propagation Delay (tpd) | — | 35 ns (max, '-35' speed grade) |
| Configuration Method | — | UV-erase + EPROM programmer |
| Development Tool (legacy) | — | MAX+PLUS II / A+PLUS |
| Lead-Free | — | [DATA_NEEDED] |