EP1810LC-35 vs EP1810LC-35T 比較
詳細並排比較 EP1810LC-35 由 Rochester Electronics 與 EP1810LC-35T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最後購買機會規格比較
| 參數 | EP1810LC-35 | EP1810LC-35T |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | — |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS |
| 封裝 | 68-pin PLCC (J-Lead) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| 安裝類型 | Surface Mount (socketable) | Surface Mount (PLCC socket or direct solder) |
| 工作溫度 | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED] | Non-compliant (legacy PLCC product) |
| Lead-Free | [DATA_NEEDED] | — |
| Device Family | — | EP1810 Classic EPLD |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |