EP1K10TC100-2 vs EP1K10TC100-3 比較

詳細並排比較 EP1K10TC100-2 由 Intel 與 EP1K10TC100-3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K10TC100-2 EP1K10TC100-3
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family ACEX-1K ACEX-1K
Device Type FPGA (Field Programmable Gate Array) —
Logic Elements / Cells 576 —
Number of Logic Array Blocks (LABs/CLBs) 72 —
Total RAM Bits 12288 12,288
Number of Gates 10000 (typical); 56000 (maximum) —
Number of User I/O 66 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Pin-to-Pin Logic Delay 0.5 ns —
Maximum Internal Frequency 200 MHz (per FPGAkey listing) —
Process Technology 0.22 μm CMOS 0.22 µm CMOS
Core Supply Voltage (VCCINT) 2.375 V to 2.625 V (2.5 V nominal) —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: VCCIO range] —
工作溫度 0 °C to 70 °C (TA, commercial) [DATA_NEEDED: operating temperature grade]
封裝 100-pin TQFP (TQFP-100) 100-pin TQFP (TQFP-100)
安裝類型 Surface Mount Surface Mount
Configuration Method SRAM, serial / JTAG (IEEE 1149.1) —
RoHS 狀態 Compliant (per Heisener / DigiKey listings) [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Number of Logic Elements (LEs) — 576
Typical Gates — 10,000
Number of LABs — 72
Number of EABs — 3
User I/O Pins — 66
Operating Frequency (max) — 200 MHz
Speed Grade — -3 (fastest commercial)
Core Voltage — 2.5 V
Programming Interface — JTAG (IEEE 1149.1)
Supported I/O Standards — LVTTL, LVCMOS, PCI
Memory Configuration — Dual-port RAM supported (per family)

資料表與資源

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