EP1K30TC144-2 vs EP1K30TI144-2NGA 比較

詳細並排比較 EP1K30TC144-2 由 Intel 與 EP1K30TI144-2NGA 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K30TC144-2 EP1K30TI144-2NGA
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family ACEX 1K —
Logic Elements / Cells 1,728 1728
System Gates 30,000 —
Logic Array Blocks (LABs) 216 —
User I/Os 102 —
Embedded Array Blocks (EABs) 6 —
Total EAB Memory 24,576 bits —
Process Technology 0.22 µm SRAM LUT 0.18 um SRAM CMOS
Core Supply Voltage (VCCINT) 2.5 V (2.375 V - 2.625 V) —
I/O Supply Voltage (VCCIO) 3.3 V (LVTTL/LVCMOS), 2.5 V, or PCI 3.3 V
Maximum Internal Clock Frequency 200 MHz —
封裝 144-pin TQFP (TC) —
Operating Temperature (Commercial) 0C to +70C —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL level] —
Configuration Method Passive Serial / JTAG / EPC1/EPC2 PROM —
RoHS 狀態 [DATA_NEEDED: RoHS status] —
Speed Grade -2 (mid commercial speed grade) -2 (faster than -3)
Series — ACEX 1K
Total RAM Bits — 24576
Number of Logic Array Blocks (LABs) — 216
Number of I/O — 102
Number of Gates (typical) — 119000
Core Voltage (VCCINT) — 2.5 V
工作溫度 — -40C to +85C (Industrial)
封裝 / 外殼 — 144-LFQFP / 144-TQFP (20x20 mm)
Programmable Logic Type — In-system programmable SRAM FPGA
Lead Free / RoHS Status — Lead free / RoHS compliant per suffix code
Design Software — Quartus II, MAX+PLUS II
JTAG Support — Yes (IEEE 1149.1 boundary scan)
Configuration — SRAM-based, requires configuration device at power-up

資料表與資源

瀏覽所有產品 建立 BOM 索取報價