EP1K50QC208-3Q vs EP1K100QC208-3N 比較

詳細並排比較 EP1K50QC208-3Q 由 Altera 與 EP1K100QC208-3N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP1K100QC208-3N EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N Obsolete

規格比較

參數 EP1K50QC208-3Q EP1K100QC208-3N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family ACEX 1K —
Logic Elements 2,880 cells —
Equivalent Gates 50,000 gates —
Embedded Memory 40,960 bits (12 EABs) —
Logic Array Blocks (LABs) 360 —
Embedded Array Blocks (EABs) 12 —
Maximum User I/O 147 —
Maximum Operating Frequency 166.67 MHz —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V tolerant —
Speed Grade -3 (standard commercial) —
封裝 208-pin PQFP (Plastic Quad Flat Pack) —
Programming Interface IEEE 1149.1 JTAG —
Operating Temperature Grade Q suffix — military/aerospace range —
安裝類型 Surface Mount Surface Mount
Product Series — ACEX-1K
Device Type — Field Programmable Gate Array (FPGA)
Number of Logic Elements — 4992
Number of LABs — 624
Embedded RAM Bits — 49152
Total Typical Gates — 100K
Number of User I/Os — 147
I/O Supply Voltage Range — [DATA_NEEDED: I/O supply voltage range]
Maximum Internal Clock Frequency — 200 MHz
Package Type — 208-BFQFP
腳位數 — 208
Terminal Form — Gull Wing
JTAG Boundary Scan — IEEE Std. 1149.1-1990 compliant built-in BST
Lead-Free Version — Yes (N suffix)
工作溫度範圍 — Commercial grade ([DATA_NEEDED: exact operating temperature range])
Supported Configuration Devices — EPC2/EPC16 family ([DATA_NEEDED: exact ACEX-1K supported list])
Moisture Sensitivity Level — [DATA_NEEDED: MSL level]
RoHS 狀態 — [DATA_NEEDED: RoHS certificate status]

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