EP1M120F484C5N vs EP1M120F484 比較

詳細並排比較 EP1M120F484C5N 由 Altera 與 EP1M120F484 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1M120F484C5N EP1M120F484
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family Mercury Mercury (EP1M)
Logic Elements / Cells 4,800 (120K equivalent gates) 4,800
Logic Array Blocks (LABs) 480 —
User I/Os 303 —
Process Technology 0.18 micron CMOS CMOS
Core Supply Voltage 1.8 V (1.71 V to 1.89 V) 1.8 V
Integrated Transceivers Yes, with CDR up to 1.25 Gbps —
封裝 484-pin FC-FBGA (FineLine BGA, 23 mm x 23 mm) 484-pin FineLine BGA (FCBGA)
安裝類型 Surface Mount Surface Mount (BGA)
工作溫度 0 C to 85 C (Commercial) Unknown [DATA_NEEDED: operating temperature range]
Speed Grade C5 —
RoHS 狀態 [DATA_NEEDED: RoHS status - not stated in retrieved data] Unknown [DATA_NEEDED: RoHS status]
MSL 等級 [DATA_NEEDED: MSL level - not stated in retrieved data] —
Lead-Free [DATA_NEEDED: lead-free status - not stated in retrieved data] —
無鹵素 [DATA_NEEDED: halogen-free status - not stated in retrieved data] —
Gate Count — 120,000
Embedded Memory (Bits) — 49,152
User I/O Pins — 303
Total Package Pins — 484
I/O Supply Voltage — 3.3 V / 2.5 V
Transceiver Channels — Up to 18 channels
Max Transceiver Data Rate — 1.25 Gbps with CDR
Speed Grade (this P/N) — Not specified in provided data [DATA_NEEDED: speed grade]
Configuration Interface — JTAG (IEEE 1149.1) / EPC serial

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