EP1S20F672C6 vs EP1S20B672C6 比較
詳細並排比較 EP1S20F672C6 由 Altera 與 EP1S20B672C6 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S20F672C6 | EP1S20B672C6 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Altera (now Intel) | Intel (formerly Altera) |
| Series | Stratix | — |
| Family | Stratix (first generation) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | — |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| Maximum User I/Os | 426 | — |
| 封裝 | 672-ball FineLine BGA | 672-ball FineLine BGA (672-BBGA) |
| Package Code | F672 | — |
| Speed Grade | C6 | C6 |
| 工作溫度 | 0°C to +85°C (Commercial) | 0 C to 85 C (commercial) |
| 供應電壓 | Core 1.5 V, I/O programmable | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Logic Elements | — | 18,460 |
| User I/O Count | — | 426 |
| Package Dimensions | — | 35 mm x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Maximum Internal Frequency | — | 450.05 MHz |
| Logic Family | — | CMOS |
| Configuration Method | — | PS / PPS / PPA / JTAG |