EP1SGX25FF1020C5N vs EP1SGX25FF1020C5L 比較

詳細並排比較 EP1SGX25FF1020C5N 由 Intel 與 EP1SGX25FF1020C5L 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Intel

EP1SGX25FF1020C5N - 25,660 Logic Elements Stratix GX FPGA | Intel

EP1SGX25FF1020C5N ⚠ 最後購買機會

Altera

EP1SGX25FF1020C5L Obsolete

參數	EP1SGX25FF1020C5N	EP1SGX25FF1020C5L
品牌	Intel	Altera
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	最後購買	Obsolete
Series	Stratix GX	—
Family	Stratix GX (Stratix I GX)	Stratix GX
Manufacturer	Intel (formerly Altera)	—
Logic Elements / Cells	25,660	—
Logic Array Blocks (LABs)	2,566	—
User I/Os	607	—
Process Technology	130 nm CMOS	130 nm CMOS
Core Voltage	1.5 V	1.5 V
工作溫度	0 °C to 85 °C (commercial)	[DATA_NEEDED: operating temperature range]
Package Type	FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)	FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array)
Package Size	33 x 33 mm	—
Ball Pitch	1.0 mm	—
Lead Free	Yes (per datasheet snippet)	—
Logic Family	CMOS	—
Speed Grade	C5 (approx. 500 MHz internal clock)	C5 (slowest tier)
安裝類型	Surface Mount	Surface Mount
RoHS 狀態	[DATA_NEEDED: confirm RoHS status - datasheet does not state explicitly]	[DATA_NEEDED: RoHS compliance]
Logic Elements	—	25,660 cells
腳位數	—	1020 balls
Maximum Transceiver Data Rate	—	3.125 Gbps
Maximum Operating Frequency	—	5000 MHz (internal reference)
Memory Architecture	—	TriMatrix (M512/M4K/M-RAM blocks)
I/O Standards Supported	—	LVDS, LVTTL, LVCMOS, HSTL, SSTL
Configuration Scheme	—	Active serial (EPCS), passive serial, JTAG
DSP Blocks	—	[DATA_NEEDED: DSP block count]