EP1SGX40DF1020C5ES vs EP1SGX40GF1020C5ES 比較
詳細並排比較 EP1SGX40DF1020C5ES 由 Intel 與 EP1SGX40GF1020C5ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1SGX40DF1020C5ES | EP1SGX40GF1020C5ES |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Logic Family | Stratix GX | CMOS |
| Logic Technology | CMOS | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Logic Cells | 41,250 cells | — |
| Logic Array Blocks | 4,125 LABs | — |
| Configurable I/O Connections | 624 input and 624 output connections | — |
| 供應電壓 | 1.5 V | — |
| Reported Maximum Frequency | 5,000 MHz | — |
| Reported Maximum CLB Combinatorial Delay | 7.49 ns | — |
| Alternative Listed Maximum Clock Frequency | 6 MHz | — |
| Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA-1020 | — |
| Package Dimensions | 33 mm x 33 mm | 33.00 mm x 33.00 mm |
| Ball Pitch | 1 mm | 1.00 mm |
| 工作溫度 | 0 C to 85 C | 0 C to +85 C (Commercial) |
| Mounting Configuration | Surface-mount ball grid array | — |
| Terminal Form | Ball | Ball |
| Package Code | BGA | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | Stratix GX |
| Logic Elements | — | 41,250 |
| Configurable Logic Blocks (CLBs) | — | 4,125 |
| Core Supply Voltage | — | 1.5 V |
| Maximum Internal Clock Frequency | — | 5,000 MHz |
| Embedded Transceivers | — | Yes, multi-gigabit (3.125 Gbps) |
| 封裝 | — | 1020-ball Flip-Chip FBGA (S-PBGA-B1020) |
| Seated Height | — | 3.50 mm |
| Number of Terminals | — | 1020 |
| Part Suffix | — | ES (Engineering Sample) |
| 安裝類型 | — | Surface Mount |