EP20K100CB356C7 vs EP20K100CF144C7 比較

詳細並排比較 EP20K100CB356C7 由 Intel 與 EP20K100CF144C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EP20K100CB356C7 EP20K100CB356C7 - APEX20K FPGA 100K Gates 252 I/O 356-BGA | Intel

EP20K100CB356C7 - APEX20K FPGA 100K Gates 252 I/O 356-BGA | Intel

EP20K100CB356C7 ⚠ 最後購買機會

規格比較

參數 EP20K100CB356C7 EP20K100CF144C7
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Manufacturer Intel (formerly Altera) —
Series APEX20K APEX-20K
Typical Gates 100,000 —
Maximum Logic Elements 53,248 —
User I/O Pins 252 —
封裝 356-LBGA —
Embedded Memory (Bits) 53,248 —
Number of PLLs 4 —
Core Voltage 2.5 V —
I/O Standards Supported 1.8V, 2.5V, 3.3V, 5V (MultiVolt) —
Programming Interface IEEE 1149.1 JTAG —
Process Technology 0.18 μm CMOS 0.18 micron CMOS SRAM
工作溫度 Commercial grade 0C to +85C (commercial)
Speed Grade C7 C7 (commercial)
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Family — APEX-20K Field Programmable Gate Array
Logic Elements / Cells — 4,160
Total RAM Bits — 53,248
Number of Logic Elements — 4,160
Number of I/O — 93
Number of Gates — 100,000 system gates
Voltage - Supply — 1.8 V core, 3.3 V I/O (typical APEX-20K rails)
安裝類型 — Surface Mount
封裝 / 外殼 — 144-LQFP
Package Dimensions — 22 x 22 mm, 0.5 mm pitch
Configuration Mode — Passive Serial, JTAG (IEEE 1149.1)
PLLs — 4 (per APEX-20K family architecture)

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