EP20K100CQ240C8ES vs EP20K100CQ240C8 比較
詳細並排比較 EP20K100CQ240C8ES 由 Intel 與 EP20K100CQ240C8 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K100CQ240C8ES | EP20K100CQ240C8 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Product Family | Intel/Altera EP20K series FPGA family | — |
| Number of Logic Elements / Cells | 4,160 | — |
| Total RAM Bits | 53,248 bits | — |
| Number of User I/O | 189 | — |
| 封裝 / 外殼 | 240-BFQFP / QFP-240 | — |
| Package Type | Quad Flat Package | — |
| Packaging | Tray | — |
| 安裝類型 | Surface Mount | — |
| Ordering/ Speed Grade Suffix | C8ES | — |
| Stock Quantity | 4,816 pieces per Heisener listing | — |
| Lead Time | To Be Confirmed | — |
| Unit Price | Request a Quote | — |
| Minimum Operating Temperature | [DATA_NEEDED: minimum operating temperature] | — |
| Maximum Operating Temperature | [DATA_NEEDED: maximum operating temperature] | — |
| Core / I/O Supply Voltage | [DATA_NEEDED: VCCINT and VCCIO voltage] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Differential I/O Pairs | [DATA_NEEDED: number of differential I/O pairs] | — |
| Configuration Schemes | [DATA_NEEDED: supported configuration schemes] | — |
| RoHS 狀態 | Unknown - not confirmed in scraped listing | [DATA_NEEDED: RoHS status] |
| Family | — | APEX 20K |
| Series | — | EP20K100 |
| Typical Gates | — | 100,000 |
| Maximum System Gates | — | 263,000 |
| Logic Elements | — | 4,160 |
| Embedded Memory (ESB) | — | 53,248 bits |
| User I/O Pins | — | 189 |
| 封裝 | — | 240-pin PQFP (QFP) |
| Speed Grade | — | C8 (commercial, -8) |
| 工作溫度 | — | 0C to +85C (commercial) |
| Core Voltage | — | 2.5 V |
| I/O Standards | — | LVTTL, LVCMOS, PCI |
| Configuration Interface | — | JTAG (IEEE 1149.1), serial/parallel |
| Programming Method | — | SRAM-based, in-system programmable |