EP20K100FC324-2X vs EP20K100FC324-1 比較

詳細並排比較 EP20K100FC324-2X 由 Altera 與 EP20K100FC324-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K100FC324-2X EP20K100FC324-1
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 停產終止
Family APEX-20K —
Logic Elements 4,160 —
Typical Gates 100,000 —
Maximum System Gates 263,000 —
Maximum User I/O 252 —
Embedded RAM Bits 53,248 —
Operating Frequency (max) 200 MHz —
Propagation Delay 1.6 ns —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage 3.3 V (5 V tolerant I/O) —
封裝 324-ball FineLine BGA (FBGA) —
安裝類型 Surface Mount Surface Mount
工作溫度 0 °C to +85 °C (Commercial) —
Configuration Interface JTAG (IEEE 1149.1) / Serial / Parallel —
RoHS 狀態 Compliant —
Product Type — Field Programmable Gate Array (FPGA)
Series — APEX-20K
Number of Logic Elements/Cells — 4160
Total RAM Bits — 53248 bits
Number of User I/Os — 252
Number of LABs/CLBs — [DATA_NEEDED: Number of LABs/CLBs]
Number of Gates — [DATA_NEEDED: Number of gates]
Maximum Internal Clock Frequency — [DATA_NEEDED: fMAX]
I/O Supply Voltage Range — [DATA_NEEDED: I/O supply voltage range]
封裝 / 外殼 — 324-BGA (FC324)
Supplier Device Package — 324-FBGA
腳位數 — 324
工作溫度範圍 — 0 °C to +85 °C
Architecture — MultiCore: LUT logic + product-term logic + embedded memory
Speed Grade — -1
Configuration Memory — SRAM-based (external configuration device required)
RoHS Compliance — Unknown; lead-free -1N suffix variant exists

資料表與資源

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