EP20K100QC240-3 vs EP20K100QC240-3N 比較
詳細並排比較 EP20K100QC240-3 由 Altera 與 EP20K100QC240-3N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K100QC240-3 | EP20K100QC240-3N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Manufacturer | Altera | — |
| FPGA Family | APEX-20K | — |
| Number of Logic Elements | 4160 cells | — |
| Total RAM Bits | 53248 bits | — |
| Number of User I/O | 189 | — |
| Typical Gate Count | 263000 gates | — |
| Core Supply Voltage | 2.5 V | — |
| 最大時脈頻率 | 167 MHz (family rating) | — |
| Speed Grade | -3 | — |
| Technology Process | 0.22 um | — |
| Package Type | 240-BFQFP | — |
| 腳位數 | 240 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | 0 °C to +85 °C (commercial) | — |
| Propagation Delay | [DATA_NEEDED: propagation delay timing table] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration / JTAG Interface | [DATA_NEEDED: configuration and JTAG interface details] | — |
| RoHS Compliance | [DATA_NEEDED: RoHS compliance for non-N version] | — |
| Device Type | — | FPGA |
| Family | — | APEX-20K |
| Gate Count | — | 100000 gates |
| Logic Cells | — | 4160 cells |
| User I/O | — | 189 I/O |
| Distributed Memory | — | 53248 bits |
| Macrocells | — | 416 macrocells |
| 供應電壓 | — | 2.375 V to 2.625 V |
| Nominal Supply | — | 2.5 V |
| Maximum Frequency | — | 167 MHz |
| 工作溫度 | — | 0 C to 85 C |
| 封裝 | — | 240-BFQFP |
| 腳位數 | — | 240 pins |
| Fabrication Process | — | 0.15 um all-layer copper-metal process |
| Package Pitch | — | 1.27 mm |
| Package Dimensions | — | 45 mm x 45 mm |
| RoHS 狀態 | — | unknown |
| AEC-Q100 | — | not_qualified |