EP20K100QC240-3N vs EP20K100QI240-2N 比較

詳細並排比較 EP20K100QC240-3N 由 Altera 與 EP20K100QI240-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Altera

EP20K100QC240-3N - 100K-Gate APEX-20K FPGA | Altera | Industrial

EP20K100QC240-3N ✓ 啟用中

Altera

EP20K100QI240-2N Obsolete

參數	EP20K100QC240-3N	EP20K100QI240-2N
品牌	Altera	Altera
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	啟用中	Obsolete
Device Type	FPGA	FPGA (Field Programmable Gate Array)
Family	APEX-20K	—
Gate Count	100000 gates	—
Logic Cells	4160 cells	—
User I/O	189 I/O	—
Distributed Memory	53248 bits	—
Macrocells	416 macrocells	—
供應電壓	2.375 V to 2.625 V	—
Nominal Supply	2.5 V	—
Maximum Frequency	167 MHz	—
工作溫度	0 C to 85 C	—
封裝	240-BFQFP	—
腳位數	240 pins	—
安裝類型	Surface Mount	Surface Mount
Fabrication Process	0.15 um all-layer copper-metal process	—
Package Pitch	1.27 mm	—
Package Dimensions	45 mm x 45 mm	—
RoHS 狀態	unknown	[DATA_NEEDED: exact RoHS certificate]
AEC-Q100	not_qualified	—
Product Family	—	APEX 20K
Total System Gates	—	100K
Logic Elements / Cells	—	4160
Embedded RAM Bits (max)	—	53248
Number of User I/Os	—	189
Number of Dedicated Inputs	—	4
Core Supply Voltage	—	2.5 V nominal (2.375 V to 2.625 V)
Process Technology	—	0.22 um CMOS
Maximum Internal Clock Frequency	—	200 MHz
Package Code	—	FQFP
Package Form	—	240-Pin PQFP, fine-pitch flatpack, square
Package Body Size	—	32 mm x 32 mm (Length 32 mm)
Terminal Pitch	—	0.5 mm
Terminal Form	—	Gull wing
MSL 等級	—	[DATA_NEEDED: exact MSL for EP20K100QI240-2N; same PQFP listing indicates MSL 3]
Operating Temperature Grade	—	Industrial (I suffix)
Core Supply Current	—	[DATA_NEEDED: ICCINT]